Microchip Technology Inc.
ATSAML10E14A
2024.06.03
Microchip ATSAML10E14A Microcontroller
CM23
r0p0
selectable
true
2
false
8
32
AC
Analog Comparators
AC
0x0
0x0
0x24
registers
n
AC
39
COMPCTRL0
Comparator Control n
0x10
32
read-write
n
0x0
0x0
ENABLE
Enable
1
1
FLEN
Filter Length
24
3
FLENSelect
OFF
No filtering
0
MAJ3
3-bit majority function (2 of 3)
1
MAJ5
5-bit majority function (3 of 5)
2
HYST
Hysteresis Level
20
2
HYSTSelect
HYST50
50mV
0
HYST70
70mV
1
HYST90
90mV
2
HYST110
110mV
3
HYSTEN
Hysteresis Enable
19
1
INTSEL
Interrupt Selection
3
2
INTSELSelect
TOGGLE
Interrupt on comparator output toggle
0
RISING
Interrupt on comparator output rising
1
FALLING
Interrupt on comparator output falling
2
EOC
Interrupt on end of comparison (single-shot mode only)
3
MUXNEG
Negative Input Mux Selection
8
3
MUXNEGSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
GND
Ground
4
VSCALE
VDD scaler
5
BANDGAP
Internal bandgap voltage
6
OPAMP
OPAMP output (on AC1)
7
DAC
DAC output (on AC0)
7
MUXPOS
Positive Input Mux Selection
12
3
MUXPOSSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
VSCALE
VDD Scaler
4
OUT
Output
28
2
OUTSelect
OFF
The output of COMPn is not routed to the COMPn I/O port
0
ASYNC
The asynchronous output of COMPn is routed to the COMPn I/O port
1
SYNC
The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
2
RUNSTDBY
Run in Standby
6
1
SINGLE
Single-Shot Mode
2
1
SPEED
Speed Selection
16
2
SPEEDSelect
LOW
Low speed
0
MEDLOW
Medium low speed
1
MEDHIGH
Medium high speed
2
HIGH
High speed
3
SWAP
Swap Inputs and Invert
15
1
COMPCTRL1
Comparator Control n
0x14
32
read-write
n
0x0
0x0
ENABLE
Enable
1
1
FLEN
Filter Length
24
3
FLENSelect
OFF
No filtering
0
MAJ3
3-bit majority function (2 of 3)
1
MAJ5
5-bit majority function (3 of 5)
2
HYST
Hysteresis Level
20
2
HYSTSelect
HYST50
50mV
0
HYST70
70mV
1
HYST90
90mV
2
HYST110
110mV
3
HYSTEN
Hysteresis Enable
19
1
INTSEL
Interrupt Selection
3
2
INTSELSelect
TOGGLE
Interrupt on comparator output toggle
0
RISING
Interrupt on comparator output rising
1
FALLING
Interrupt on comparator output falling
2
EOC
Interrupt on end of comparison (single-shot mode only)
3
MUXNEG
Negative Input Mux Selection
8
3
MUXNEGSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
GND
Ground
4
VSCALE
VDD scaler
5
BANDGAP
Internal bandgap voltage
6
OPAMP
OPAMP output (on AC1)
7
DAC
DAC output (on AC0)
7
MUXPOS
Positive Input Mux Selection
12
3
MUXPOSSelect
PIN0
I/O pin 0
0
PIN1
I/O pin 1
1
PIN2
I/O pin 2
2
PIN3
I/O pin 3
3
VSCALE
VDD Scaler
4
OUT
Output
28
2
OUTSelect
OFF
The output of COMPn is not routed to the COMPn I/O port
0
ASYNC
The asynchronous output of COMPn is routed to the COMPn I/O port
1
SYNC
The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
2
RUNSTDBY
Run in Standby
6
1
SINGLE
Single-Shot Mode
2
1
SPEED
Speed Selection
16
2
SPEEDSelect
LOW
Low speed
0
MEDLOW
Medium low speed
1
MEDHIGH
Medium high speed
2
HIGH
High speed
3
SWAP
Swap Inputs and Invert
15
1
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
SWRST
Software Reset
0
1
CTRLB
Control B
0x1
8
write-only
n
0x0
0x0
START0
Comparator 0 Start Comparison
0
1
START1
Comparator 1 Start Comparison
1
1
DBGCTRL
Debug Control
0x9
8
read-write
n
0x0
0x0
DBGRUN
Debug Run
0
1
EVCTRL
Event Control
0x2
16
read-write
n
0x0
0x0
COMPEI0
Comparator 0 Event Input Enable
8
1
COMPEI1
Comparator 1 Event Input Enable
9
1
COMPEO0
Comparator 0 Event Output Enable
0
1
COMPEO1
Comparator 1 Event Output Enable
1
1
INVEI0
Comparator 0 Input Event Invert Enable
12
1
INVEI1
Comparator 1 Input Event Invert Enable
13
1
WINEO0
Window 0 Event Output Enable
4
1
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
COMP0
Comparator 0 Interrupt Enable
0
1
COMP1
Comparator 1 Interrupt Enable
1
1
WIN0
Window 0 Interrupt Enable
4
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
COMP0
Comparator 0 Interrupt Enable
0
1
COMP1
Comparator 1 Interrupt Enable
1
1
WIN0
Window 0 Interrupt Enable
4
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
COMP0
Comparator 0
0
1
COMP1
Comparator 1
1
1
WIN0
Window 0
4
1
SCALER0
Scaler n
0xC
8
read-write
n
0x0
0x0
VALUE
Scaler Value
0
6
SCALER1
Scaler n
0xD
8
read-write
n
0x0
0x0
VALUE
Scaler Value
0
6
STATUSA
Status A
0x7
8
read-only
n
0x0
0x0
STATE0
Comparator 0 Current State
0
1
STATE1
Comparator 1 Current State
1
1
WSTATE0
Window 0 Current State
4
2
WSTATE0Select
ABOVE
Signal is above window
0
INSIDE
Signal is inside window
1
BELOW
Signal is below window
2
STATUSB
Status B
0x8
8
read-only
n
0x0
0x0
READY0
Comparator 0 Ready
0
1
READY1
Comparator 1 Ready
1
1
SYNCBUSY
Synchronization Busy
0x20
32
read-only
n
0x0
0x0
COMPCTRL0
COMPCTRL 0 Synchronization Busy
3
1
COMPCTRL1
COMPCTRL 1 Synchronization Busy
4
1
ENABLE
Enable Synchronization Busy
1
1
SWRST
Software Reset Synchronization Busy
0
1
WINCTRL
WINCTRL Synchronization Busy
2
1
WINCTRL
Window Control
0xA
8
read-write
n
0x0
0x0
WEN0
Window 0 Mode Enable
0
1
WINTSEL0
Window 0 Interrupt Selection
1
2
WINTSEL0Select
ABOVE
Interrupt on signal above window
0
INSIDE
Interrupt on signal inside window
1
BELOW
Interrupt on signal below window
2
OUTSIDE
Interrupt on signal outside window
3
ADC
Analog Digital Converter
ADC
0x0
0x0
0x2E
registers
n
ADC_OTHER
37
ADC_RESRDY
38
AVGCTRL
Average Control
0xC
8
read-write
n
0x0
0x0
ADJRES
Adjusting Result / Division Coefficient
4
3
SAMPLENUM
Number of Samples to be Collected
0
4
SAMPLENUMSelect
1
1 sample
0x0
2
2 samples
0x1
4
4 samples
0x2
8
8 samples
0x3
16
16 samples
0x4
32
32 samples
0x5
64
64 samples
0x6
128
128 samples
0x7
256
256 samples
0x8
512
512 samples
0x9
1024
1024 samples
0xA
CALIB
Calibration
0x2C
16
read-write
n
0x0
0x0
BIASCOMP
Bias Comparator Scaling
0
3
BIASREFBUF
Bias Reference Buffer Scaling
8
3
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run During Standby
6
1
SLAVEEN
Slave Enable
5
1
SWRST
Software Reset
0
1
CTRLB
Control B
0x1
8
read-write
n
0x0
0x0
PRESCALER
Prescaler Configuration
0
3
PRESCALERSelect
DIV2
Peripheral clock divided by 2
0x0
DIV4
Peripheral clock divided by 4
0x1
DIV8
Peripheral clock divided by 8
0x2
DIV16
Peripheral clock divided by 16
0x3
DIV32
Peripheral clock divided by 32
0x4
DIV64
Peripheral clock divided by 64
0x5
DIV128
Peripheral clock divided by 128
0x6
DIV256
Peripheral clock divided by 256
0x7
CTRLC
Control C
0xA
16
read-write
n
0x0
0x0
CORREN
Digital Correction Logic Enable
3
1
DIFFMODE
Differential Mode
0
1
DUALSEL
Dual Mode Trigger Selection
12
2
DUALSELSelect
BOTH
Start event or software trigger will start a conversion on both ADCs
0
INTERLEAVE
START event or software trigger will alternatingly start a conversion on ADC0 and ADC1
1
FREERUN
Free Running Mode
2
1
LEFTADJ
Left-Adjusted Result
1
1
R2R
Rail-to-Rail mode enable
7
1
RESSEL
Conversion Result Resolution
4
2
RESSELSelect
12BIT
12-bit result
0x0
16BIT
Accumulation or Oversampling and Decimation modes
0x1
10BIT
10-bit result
0x2
8BIT
8-bit result
0x3
WINMODE
Window Monitor Mode
8
3
WINMODESelect
DISABLE
No window mode (default)
0
MODE1
RESULT > WINLT
1
MODE2
RESULT < WINUT
2
MODE3
WINLT < RESULT < WINUT
3
MODE4
!(WINLT < RESULT < WINUT)
4
DBGCTRL
Debug Control
0x1C
8
read-write
n
0x0
0x0
DBGRUN
Debug Run
0
1
EVCTRL
Event Control
0x3
8
read-write
n
0x0
0x0
FLUSHEI
Flush Event Input Enable
0
1
FLUSHINV
Flush Event Invert Enable
2
1
RESRDYEO
Result Ready Event Out
4
1
STARTEI
Start Conversion Event Input Enable
1
1
STARTINV
Satrt Event Invert Enable
3
1
WINMONEO
Window Monitor Event Out
5
1
GAINCORR
Gain Correction
0x12
16
read-write
n
0x0
0x0
GAINCORR
Gain Correction Value
0
12
INPUTCTRL
Input Control
0x8
16
read-write
n
0x0
0x0
MUXNEG
Negative Mux Input Selection
8
5
MUXNEGSelect
AIN0
ADC AIN0 Pin
0x0
AIN1
ADC AIN1 Pin
0x1
GND
Internal Ground
0x18
AIN2
ADC AIN2 Pin
0x2
AIN3
ADC AIN3 Pin
0x3
AIN4
ADC AIN4 Pin
0x4
AIN5
ADC AIN5 Pin
0x5
AIN6
ADC AIN6 Pin
0x6
AIN7
ADC AIN7 Pin
0x7
MUXPOS
Positive Mux Input Selection
0
5
MUXPOSSelect
AIN0
ADC AIN0 Pin
0x0
AIN1
ADC AIN1 Pin
0x1
AIN16
ADC AIN16 Pin
0x10
AIN17
ADC AIN17 Pin
0x11
AIN18
ADC AIN18 Pin
0x12
AIN19
ADC AIN19 Pin
0x13
AIN20
ADC AIN20 Pin
0x14
AIN21
ADC AIN21 Pin
0x15
AIN22
ADC AIN22 Pin
0x16
AIN23
ADC AIN23 Pin
0x17
TEMP
Temperature Sensor
0x18
BANDGAP
Bandgap Voltage
0x19
SCALEDCOREVCC
1/4 Scaled Core Supply
0x1A
SCALEDVDDCORE
1/4 Scaled VDDCORE Supply
0x1A
SCALEDIOVCC
1/4 Scaled I/O Supply
0x1B
SCALEDVDDANA
1/4 Scaled VDDANA Supply
0x1B
DAC
DAC Output
0x1C
SCALEDVBAT
1/4 Scaled VBAT Supply
0x1D
SCALEDVDDIO
1/4 Scaled VDDIO Supply
0x1D
OPAMP01
OPAMP0 or OPAMP1 output
0x1E
OPAMP2
OPAMP2 output
0x1F
AIN2
ADC AIN2 Pin
0x2
AIN3
ADC AIN3 Pin
0x3
AIN4
ADC AIN4 Pin
0x4
AIN5
ADC AIN5 Pin
0x5
AIN6
ADC AIN6 Pin
0x6
AIN7
ADC AIN7 Pin
0x7
AIN8
ADC AIN8 Pin
0x8
AIN9
ADC AIN9 Pin
0x9
AIN10
ADC AIN10 Pin
0xA
AIN11
ADC AIN11 Pin
0xB
AIN12
ADC AIN12 Pin
0xC
AIN13
ADC AIN13 Pin
0xD
AIN14
ADC AIN14 Pin
0xE
AIN15
ADC AIN15 Pin
0xF
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
OVERRUN
Overrun Interrupt Disable
1
1
RESRDY
Result Ready Interrupt Disable
0
1
WINMON
Window Monitor Interrupt Disable
2
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
OVERRUN
Overrun Interrupt Enable
1
1
RESRDY
Result Ready Interrupt Enable
0
1
WINMON
Window Monitor Interrupt Enable
2
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
OVERRUN
Overrun Interrupt Flag
1
1
RESRDY
Result Ready Interrupt Flag
0
1
WINMON
Window Monitor Interrupt Flag
2
1
OFFSETCORR
Offset Correction
0x14
16
read-write
n
0x0
0x0
OFFSETCORR
Offset Correction Value
0
12
REFCTRL
Reference Control
0x2
8
read-write
n
0x0
0x0
REFCOMP
Reference Buffer Offset Compensation Enable
7
1
REFSEL
Reference Selection
0
4
REFSELSelect
INTREF
Internal Bandgap Reference
0x0
INTVCC0
1/1.6 VDDANA
0x1
INTVCC1
1/2 VDDANA
0x2
AREFA
External Reference
0x3
VREFA
External Reference
0x3
AREFB
External Reference
0x4
VREFB
External Reference
0x4
INTVCC2
VDDANA
0x5
RESULT
Result
0x24
16
read-only
n
0x0
0x0
RESULT
Result Value
0
16
SAMPCTRL
Sample Time Control
0xD
8
read-write
n
0x0
0x0
OFFCOMP
Comparator Offset Compensation Enable
7
1
SAMPLEN
Sampling Time Length
0
6
SEQCTRL
Sequence Control
0x28
32
read-write
n
0x0
0x0
SEQEN
Enable Positive Input in the Sequence
0
32
SEQSTATUS
Sequence Status
0x7
8
read-only
n
0x0
0x0
SEQBUSY
Sequence Busy
7
1
SEQSTATE
Sequence State
0
5
SWTRIG
Software Trigger
0x18
8
read-write
n
0x0
0x0
FLUSH
ADC Flush
0
1
START
Start ADC Conversion
1
1
SYNCBUSY
Synchronization Busy
0x20
16
read-only
n
0x0
0x0
AVGCTRL
AVGCTRL Synchronization Busy
4
1
CTRLC
CTRLC Synchronization Busy
3
1
ENABLE
ENABLE Synchronization Busy
1
1
GAINCORR
GAINCORR Synchronization Busy
8
1
INPUTCTRL
INPUTCTRL Synchronization Busy
2
1
OFFSETCORR
OFFSETCTRL Synchronization Busy
9
1
SAMPCTRL
SAMPCTRL Synchronization Busy
5
1
SWRST
SWRST Synchronization Busy
0
1
SWTRIG
SWTRG Synchronization Busy
10
1
WINLT
WINLT Synchronization Busy
6
1
WINUT
WINUT Synchronization Busy
7
1
WINLT
Window Monitor Lower Threshold
0xE
16
read-write
n
0x0
0x0
WINLT
Window Lower Threshold
0
16
WINUT
Window Monitor Upper Threshold
0x10
16
read-write
n
0x0
0x0
WINUT
Window Upper Threshold
0
16
CCL
Configurable Custom Logic
CCL
0x0
0x0
0x10
registers
n
CTRL
Control
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
ENABLESelect
DISABLE
The peripheral is disabled
0
ENABLE
The peripheral is enabled
1
RUNSTDBY
Run in Standby
6
1
RUNSTDBYSelect
DISABLE
Generic clock is not required in standby sleep mode
0
ENABLE
Generic clock is required in standby sleep mode
1
SWRST
Software Reset
0
1
SWRSTSelect
DISABLE
The peripheral is not reset
0
ENABLE
The peripheral is reset
1
LUTCTRL0
LUT Control x
0x8
32
read-write
n
0x0
0x0
EDGESEL
Edge Selection
7
1
EDGESELSelect
DISABLE
Edge detector is disabled
0
ENABLE
Edge detector is enabled
1
ENABLE
LUT Enable
1
1
ENABLESelect
DISABLE
LUT block is disabled
0
ENABLE
LUT block is enabled
1
FILTSEL
Filter Selection
4
2
FILTSELSelect
DISABLE
Filter disabled
0
SYNCH
Synchronizer enabled
1
FILTER
Filter enabled
2
INSEL0
Input Selection 0
8
4
INSEL0Select
MASK
Masked input
0
ASYNCEVENT
Asynchronous event input source
0xB
FEEDBACK
Feedback input source
1
ALT2TC
Alternate 2 TC input source
10
LINK
Linked LUT input source
2
EVENT
Event input source
3
IO
I/O pin input source
4
AC
AC input source
5
TC
TC input source
6
ALTTC
Alternate TC input source
7
TCC
TCC input source
8
SERCOM
SERCOM input source
9
INSEL1
Input Selection 1
12
4
INSEL1Select
MASK
Masked input
0
TCC
TCC input source
0x8
ALT2TC
Alternate 2 TC input source
0xA
ASYNCEVENT
Asynchronous event input source
0xB
FEEDBACK
Feedback input source
1
LINK
Linked LUT input source
2
EVENT
Event input source
3
IO
I/O pin input source
4
AC
AC input source
5
TC
TC input source
6
ALTTC
Alternate TC input source
7
SERCOM
SERCOM input source
9
INSEL2
Input Selection 2
16
4
INSEL2Select
MASK
Masked input
0
TCC
TCC input source
0x8
ALT2TC
Alternate 2 TC input source
0xA
ASYNCEVENT
Asynchronous event input source
0xB
FEEDBACK
Feedback input source
1
LINK
Linked LUT input source
2
EVENT
Event input source
3
IO
I/O pin input source
4
AC
AC input source
5
TC
TC input source
6
ALTTC
Alternate TC input source
7
SERCOM
SERCOM input source
9
INVEI
Inverted Event Input Enable
20
1
INVEISelect
NORMAL
Incoming event is not inverted
0
INVERTED
Incoming event is inverted
1
LUTEI
LUT Event Input Enable
21
1
LUTEISelect
DISABLE
LUT incoming event is disabled
0
ENABLE
LUT incoming event is enabled
1
LUTEO
LUT Event Output Enable
22
1
LUTEOSelect
DISABLE
LUT event output is disabled
0
ENABLE
LUT event output is enabled
1
TRUTH
Truth Value
24
8
LUTCTRL1
LUT Control x
0xC
32
read-write
n
0x0
0x0
EDGESEL
Edge Selection
7
1
EDGESELSelect
DISABLE
Edge detector is disabled
0
ENABLE
Edge detector is enabled
1
ENABLE
LUT Enable
1
1
ENABLESelect
DISABLE
LUT block is disabled
0
ENABLE
LUT block is enabled
1
FILTSEL
Filter Selection
4
2
FILTSELSelect
DISABLE
Filter disabled
0
SYNCH
Synchronizer enabled
1
FILTER
Filter enabled
2
INSEL0
Input Selection 0
8
4
INSEL0Select
MASK
Masked input
0
ASYNCEVENT
Asynchronous event input source
0xB
FEEDBACK
Feedback input source
1
ALT2TC
Alternate 2 TC input source
10
LINK
Linked LUT input source
2
EVENT
Event input source
3
IO
I/O pin input source
4
AC
AC input source
5
TC
TC input source
6
ALTTC
Alternate TC input source
7
TCC
TCC input source
8
SERCOM
SERCOM input source
9
INSEL1
Input Selection 1
12
4
INSEL1Select
MASK
Masked input
0
TCC
TCC input source
0x8
ALT2TC
Alternate 2 TC input source
0xA
ASYNCEVENT
Asynchronous event input source
0xB
FEEDBACK
Feedback input source
1
LINK
Linked LUT input source
2
EVENT
Event input source
3
IO
I/O pin input source
4
AC
AC input source
5
TC
TC input source
6
ALTTC
Alternate TC input source
7
SERCOM
SERCOM input source
9
INSEL2
Input Selection 2
16
4
INSEL2Select
MASK
Masked input
0
TCC
TCC input source
0x8
ALT2TC
Alternate 2 TC input source
0xA
ASYNCEVENT
Asynchronous event input source
0xB
FEEDBACK
Feedback input source
1
LINK
Linked LUT input source
2
EVENT
Event input source
3
IO
I/O pin input source
4
AC
AC input source
5
TC
TC input source
6
ALTTC
Alternate TC input source
7
SERCOM
SERCOM input source
9
INVEI
Inverted Event Input Enable
20
1
INVEISelect
NORMAL
Incoming event is not inverted
0
INVERTED
Incoming event is inverted
1
LUTEI
LUT Event Input Enable
21
1
LUTEISelect
DISABLE
LUT incoming event is disabled
0
ENABLE
LUT incoming event is enabled
1
LUTEO
LUT Event Output Enable
22
1
LUTEOSelect
DISABLE
LUT event output is disabled
0
ENABLE
LUT event output is enabled
1
TRUTH
Truth Value
24
8
SEQCTRL1
SEQ Control x
0x4
8
read-write
n
0x0
0x0
SEQSEL
Sequential Selection
0
4
SEQSELSelect
DISABLE
Sequential logic is disabled
0
DFF
D flip flop
1
JK
JK flip flop
2
LATCH
D latch
3
RS
RS latch
4
CoreDebug
Debug Control Block
CoreDebug
0x0
0x0
0x1C
registers
n
DCRSR
Debug Core Register Select Register
0x4
32
write-only
n
0x0
0x0
REGSEL
Register selector
0
7
REGWnR
Register write/not-read access
16
1
DEMCR
Debug Exception and Monitor Control Register
0xC
32
read-write
n
0x0
0x0
MON_EN
DebugMonitor enable
16
1
MON_PEND
DebugMonitor pending state
17
1
MON_REQ
DebugMonitor semaphore bit
19
1
MON_STEP
Enable DebugMonitor stepping
18
1
SDME
Secure DebugMonitor enable
20
1
TRCENA
Global DWT and ITM features enable
24
1
VC_BUSERR
BusFault exception Halting debug vector catch enable
8
1
VC_CHKERR
UsageFault exception checking error Halting debug vector catch enable
6
1
VC_CORERESET
Core reset Halting debug vector catch enable
0
1
VC_HARDERR
HardFault exception Halting debug vector catch enable
10
1
VC_INTERR
Excception entry and return faults Halting debug vector catch enable
9
1
VC_MMERR
MemManage exception Halting debug vector catch enable
4
1
VC_NOCPERR
UsageFault exception coprocessor access Halting debug vector catch enable
5
1
VC_SFERR
SecureFault exception Halting debug vector catch enable
11
1
VC_STATERR
UsageFault exception state information error Halting debug vector catch enable
7
1
DHCSR
Debug Halting Control and Status Register
0x0
32
read-write
n
0x0
0x0
C_DEBUGEN
Enable Halting debug
0
1
C_HALT
Halt processor
1
1
C_MASKINTS
Mask PendSV, SysTick and external configurable interrupts
3
1
C_STEP
Enable single step
2
1
S_HALT
Halted status
17
1
S_LOCKUP
Lockup status
19
1
S_REGRDY
Register ready status
16
1
S_RESET_ST
Reset sticky status
25
1
S_RESTART_ST
Restart sticky status
26
1
S_RETIRE_ST
Retire sticky status
24
1
S_SDE
Secure debug enabled
20
1
S_SLEEP
Sleeping status
18
1
S_SNAPSTALL
Snap stall control
5
1
DSCSR
Debug Security Control and Status Register
0x18
32
read-write
n
0x0
0x0
CDS
Current domain Secure
16
1
CDSKEY
CDS field write-enable key
17
1
SBRSEL
Secure Banked register select
1
1
SBRSELEN
Secure Banked register select enable
0
1
DAC
Digital Analog Converter
DAC
0x0
0x0
0x15
registers
n
DAC_UNDERRUN_A
40
DAC_EMPTY
41
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
RUNSTDBY
Run in Standby
6
1
SWRST
Software Reset
0
1
CTRLB
Control B
0x1
8
read-write
n
0x0
0x0
DITHER
Dither Enable
5
1
EOEN
External Output Enable
0
1
IOEN
Internal Output Enable
1
1
LEFTADJ
Left Adjusted Data
2
1
REFSEL
Reference Selection
6
2
REFSELSelect
INT1V
Internal 1.0V reference
0
INTREF
Internal Voltage reference
0
AVCC
AVCC
1
VDDANA
Analog Voltage Supply
1
VREFP
External reference
2
VREFA
External reference
2
VPD
Voltage Pump Disable
3
1
DATA
Data
0x8
16
write-only
n
0x0
0x0
DATA
Data value to be converted
0
16
DATABUF
Data Buffer
0xC
16
write-only
n
0x0
0x0
DATABUF
Data Buffer
0
16
DBGCTRL
Debug Control
0x14
8
read-write
n
0x0
0x0
DBGRUN
Debug Run
0
1
EVCTRL
Event Control
0x2
8
read-write
n
0x0
0x0
EMPTYEO
Data Buffer Empty Event Output
1
1
INVEI
Invert Event Input
2
1
STARTEI
Start Conversion Event Input
0
1
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
EMPTY
Data Buffer Empty Interrupt Enable
1
1
UNDERRUN
Underrun Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
EMPTY
Data Buffer Empty Interrupt Enable
1
1
UNDERRUN
Underrun Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
EMPTY
Data Buffer Empty
1
1
UNDERRUN
Underrun
0
1
STATUS
Status
0x7
8
read-only
n
0x0
0x0
READY
Ready
0
1
SYNCBUSY
Synchronization Busy
0x10
32
read-only
n
0x0
0x0
DATA
Data
2
1
DATABUF
Data Buffer
3
1
ENABLE
Enable
1
1
SWRST
Software Reset
0
1
DIB
Debug Identification Block
DIB
0x0
0x0
0x50
registers
n
DAUTHSTATUS
Debug Authentication Status Register
0x8
32
read-only
n
0x0
0x0
SID
4
2
SIDSelect
NOSEC
Security Extension not implemented
0
NO
Secure invasive debug prohibited
2
YES
Secure invasive debug allowed
3
SNID
6
2
SNIDSelect
NOSEC
Security Extension not implemented
0
NO
Secure non-invasive debug prohibited
2
YES
Secure non-invasive debug allowed
3
DCIDR0
SCS Component Identification Register 0
0x40
32
read-only
n
0x0
0x0
PRMBL_0
CoreSight component identification preamble
0
8
DCIDR1
SCS Component Identification Register 1
0x44
32
read-only
n
0x0
0x0
CLASS
CoreSight component class
4
4
PRMBL_1
CoreSight component identification preamble
0
4
DCIDR2
SCS Component Identification Register 2
0x48
32
read-only
n
0x0
0x0
PRMBL_2
CoreSight component identification preamble
0
8
DCIDR3
SCS Component Identification Register 3
0x4C
32
read-only
n
0x0
0x0
PRMBL_3
CoreSight component identification preamble
0
8
DDEVARCH
SCS Device Architecture Register
0xC
32
read-only
n
0x0
0x0
ARCHITECT
Architect
21
11
ARCHPART
Architecture Part
0
12
ARCHVER
Architecture Version
12
4
PRESENT
DEVARCH Present
20
1
REVISION
Revision
16
4
DDEVTYPE
SCS Device Type Register
0x1C
32
read-only
n
0x0
0x0
MAJOR
Major type
0
4
SUB
Sub-type
4
4
DLAR
SCS Software Lock Access Register
0x0
32
write-only
n
0x0
0x0
KEY
Lock access control
0
32
KEYSelect
UNLOCK
Unlock key value
0xC5ACCE55
DLSR
SCS Software Lock Status Register
0x4
32
read-only
n
0x0
0x0
nTT
Not thirty-two bit
2
1
SLI
Software Lock implemented
0
1
SLK
Software Lock status
1
1
DPIDR0
SCS Peripheral Identification Register 0
0x30
32
read-only
n
0x0
0x0
PART_0
Part number bits[7:0]
0
8
DPIDR1
SCS Peripheral Identification Register 1
0x34
32
read-only
n
0x0
0x0
DES_0
JEP106 identification code bits [3:0]
4
4
PART_1
Part number bits[11:8]
0
4
DPIDR2
SCS Peripheral Identification Register 2
0x38
32
read-only
n
0x0
0x0
DES_1
JEP106 identification code bits[6:4]
0
3
JEDEC
JEDEC assignee value is used
3
1
REVISION
Component revision
4
4
DPIDR3
SCS Peripheral Identification Register 3
0x3C
32
read-only
n
0x0
0x0
CMOD
Customer Modified
0
4
REVAND
RevAnd
4
4
DPIDR4
SCS Peripheral Identification Register 4
0x20
32
read-only
n
0x0
0x0
DES_2
JEP106 continuation code
0
4
SIZE
4KB count
4
4
DPIDR5
SCS Peripheral Identification Register 5
0x24
32
read-only
n
0x0
0x0
DPIDR6
SCS Peripheral Identification Register 6
0x28
32
read-only
n
0x0
0x0
DPIDR7
SCS Peripheral Identification Register 7
0x2C
32
read-only
n
0x0
0x0
DMAC
Direct Memory Access Controller
DMAC
0x0
0x0
0x50
registers
n
DMAC_0
11
DMAC_1
12
DMAC_2
13
DMAC_3
14
DMAC_OTHER
15
ACTIVE
Active Channel and Levels
0x30
32
read-only
n
0x0
0x0
ABUSY
Active Channel Busy
15
1
BTCNT
Active Channel Block Transfer Count
16
16
ID
Active Channel ID
8
5
LVLEX0
Level 0 Channel Trigger Request Executing
0
1
LVLEX1
Level 1 Channel Trigger Request Executing
1
1
LVLEX2
Level 2 Channel Trigger Request Executing
2
1
LVLEX3
Level 3 Channel Trigger Request Executing
3
1
BASEADDR
Descriptor Memory Section Base Address
0x34
32
read-write
n
0x0
0x0
BASEADDR
Descriptor Memory Base Address
0
32
BUSYCH
Busy Channels
0x28
32
read-only
n
0x0
0x0
BUSYCH0
Busy Channel 0
0
1
BUSYCH1
Busy Channel 1
1
1
BUSYCH2
Busy Channel 2
2
1
BUSYCH3
Busy Channel 3
3
1
BUSYCH4
Busy Channel 4
4
1
BUSYCH5
Busy Channel 5
5
1
BUSYCH6
Busy Channel 6
6
1
BUSYCH7
Busy Channel 7
7
1
CHCTRLA
Channel Control A
0x40
8
read-write
n
0x0
0x0
ENABLE
Channel Enable
1
1
RUNSTDBY
Channel run in standby
6
1
SWRST
Channel Software Reset
0
1
CHCTRLB
Channel Control B
0x44
32
read-write
n
0x0
0x0
CMD
Software Command
24
2
CMDSelect
NOACT
No action
0x0
SUSPEND
Channel suspend operation
0x1
RESUME
Channel resume operation
0x2
EVACT
Event Input Action
0
3
EVACTSelect
NOACT
No action
0x0
TRIG
Transfer and periodic transfer trigger
0x1
CTRIG
Conditional transfer trigger
0x2
CBLOCK
Conditional block transfer
0x3
SUSPEND
Channel suspend operation
0x4
RESUME
Channel resume operation
0x5
SSKIP
Skip next block suspend action
0x6
EVIE
Channel Event Input Enable
3
1
EVOE
Channel Event Output Enable
4
1
LVL
Channel Arbitration Level
5
2
TRIGACT
Trigger Action
22
2
TRIGACTSelect
BLOCK
One trigger required for each block transfer
0x0
BEAT
One trigger required for each beat transfer
0x2
TRANSACTION
One trigger required for each transaction
0x3
TRIGSRC
Trigger Source
8
5
TRIGSRCSelect
DISABLE
Only software/event triggers
0x00
RTC_TIMESTAMP
RTC Timestamp Trigger
0x01
DSU_DCC0
ID for DCC0 register
0x02
DSU_DCC1
ID for DCC1 register
0x03
SERCOM0_RX
SERCOM0 RX Trigger
0x04
SERCOM0_TX
SERCOM0 TX Trigger
0x05
SERCOM1_RX
SERCOM1 RX Trigger
0x06
SERCOM1_TX
SERCOM1 TX Trigger
0x07
SERCOM2_RX
SERCOM2 RX Trigger
0x08
SERCOM2_TX
SERCOM2 TX Trigger
0x09
TC0_OVF
TC0 Overflow Trigger
0x0A
TC0_MC0
TC0 Match/Compare 0 Trigger
0x0B
TC0_MC1
TC0 Match/Compare 1 Trigger
0x0C
TC1_OVF
TC1 Overflow Trigger
0x0D
TC1_MC0
TC1 Match/Compare 0 Trigger
0x0E
TC1_MC1
TC1 Match/Compare 1 Trigger
0x0F
TC2_OVF
TC2 Overflow Trigger
0x10
TC2_MC0
TC2 Match/Compare 0 Trigger
0x11
TC2_MC1
TC2 Match/Compare 1 Trigger
0x12
ADC_RESRDY
ADC Result Ready Trigger
0x13
DAC_EMPTY
DAC Empty Trigger
0x14
PTC_EOC
PTC End of Conversion Trigger
0x15
PTC_SEQ
PTC Sequence Trigger
0x16
PTC_WCOMP
PTC Window Compare Trigger
0x17
CHID
Channel ID
0x3F
8
read-write
n
0x0
0x0
ID
Channel ID
0
3
CHINTENCLR
Channel Interrupt Enable Clear
0x4C
8
read-write
n
0x0
0x0
SUSP
Channel Suspend Interrupt Enable
2
1
TCMPL
Channel Transfer Complete Interrupt Enable
1
1
TERR
Channel Transfer Error Interrupt Enable
0
1
CHINTENSET
Channel Interrupt Enable Set
0x4D
8
read-write
n
0x0
0x0
SUSP
Channel Suspend Interrupt Enable
2
1
TCMPL
Channel Transfer Complete Interrupt Enable
1
1
TERR
Channel Transfer Error Interrupt Enable
0
1
CHINTFLAG
Channel Interrupt Flag Status and Clear
0x4E
8
read-write
n
0x0
0x0
SUSP
Channel Suspend
2
1
TCMPL
Channel Transfer Complete
1
1
TERR
Channel Transfer Error
0
1
CHSTATUS
Channel Status
0x4F
8
read-only
n
0x0
0x0
BUSY
Channel Busy
1
1
FERR
Channel Fetch Error
2
1
PEND
Channel Pending
0
1
CRCCHKSUM
CRC Checksum
0x8
32
read-write
n
0x0
0x0
CRCCHKSUM
CRC Checksum
0
32
CRCCTRL
CRC Control
0x2
16
read-write
n
0x0
0x0
CRCBEATSIZE
CRC Beat Size
0
2
CRCBEATSIZESelect
BYTE
8-bit bus transfer
0x0
HWORD
16-bit bus transfer
0x1
WORD
32-bit bus transfer
0x2
CRCPOLY
CRC Polynomial Type
2
2
CRCPOLYSelect
CRC16
CRC-16 (CRC-CCITT)
0x0
CRC32
CRC32 (IEEE 802.3)
0x1
CRCSRC
CRC Input Source
8
6
CRCSRCSelect
NOACT
No action
0x00
IO
I/O interface
0x01
CHN0
DMA Channel 0
0x20
CHN1
DMA Channel 1
0x21
CHN2
DMA Channel 2
0x22
CHN3
DMA Channel 3
0x23
CHN4
DMA Channel 4
0x24
CHN5
DMA Channel 5
0x25
CHN6
DMA Channel 6
0x26
CHN7
DMA Channel 7
0x27
CRCDATAIN
CRC Data Input
0x4
32
read-write
n
0x0
0x0
CRCDATAIN
CRC Data Input
0
32
CRCSTATUS
CRC Status
0xC
8
read-write
n
0x0
0x0
CRCBUSY
CRC Module Busy
0
1
CRCZERO
CRC Zero
1
1
CTRL
Control
0x0
16
read-write
n
0x0
0x0
CRCENABLE
CRC Enable
2
1
DMAENABLE
DMA Enable
1
1
LVLEN0
Priority Level 0 Enable
8
1
LVLEN1
Priority Level 1 Enable
9
1
LVLEN2
Priority Level 2 Enable
10
1
LVLEN3
Priority Level 3 Enable
11
1
SWRST
Software Reset
0
1
DBGCTRL
Debug Control
0xD
8
read-write
n
0x0
0x0
DBGRUN
Debug Run
0
1
INTPEND
Interrupt Pending
0x20
16
read-write
n
0x0
0x0
BUSY
Busy
14
1
FERR
Fetch Error
13
1
ID
Channel ID
0
3
PEND
Pending
15
1
SUSP
Channel Suspend
10
1
TCMPL
Transfer Complete
9
1
TERR
Transfer Error
8
1
INTSTATUS
Interrupt Status
0x24
32
read-only
n
0x0
0x0
CHINT0
Channel 0 Pending Interrupt
0
1
CHINT1
Channel 1 Pending Interrupt
1
1
CHINT2
Channel 2 Pending Interrupt
2
1
CHINT3
Channel 3 Pending Interrupt
3
1
CHINT4
Channel 4 Pending Interrupt
4
1
CHINT5
Channel 5 Pending Interrupt
5
1
CHINT6
Channel 6 Pending Interrupt
6
1
CHINT7
Channel 7 Pending Interrupt
7
1
PENDCH
Pending Channels
0x2C
32
read-only
n
0x0
0x0
PENDCH0
Pending Channel 0
0
1
PENDCH1
Pending Channel 1
1
1
PENDCH2
Pending Channel 2
2
1
PENDCH3
Pending Channel 3
3
1
PENDCH4
Pending Channel 4
4
1
PENDCH5
Pending Channel 5
5
1
PENDCH6
Pending Channel 6
6
1
PENDCH7
Pending Channel 7
7
1
PRICTRL0
Priority Control 0
0x14
32
read-write
n
0x0
0x0
LVLPRI0
Level 0 Channel Priority Number
0
3
LVLPRI1
Level 1 Channel Priority Number
8
3
LVLPRI2
Level 2 Channel Priority Number
16
3
LVLPRI3
Level 3 Channel Priority Number
24
3
RRLVLEN0
Level 0 Round-Robin Scheduling Enable
7
1
RRLVLEN1
Level 1 Round-Robin Scheduling Enable
15
1
RRLVLEN2
Level 2 Round-Robin Scheduling Enable
23
1
RRLVLEN3
Level 3 Round-Robin Scheduling Enable
31
1
QOSCTRL
QOS Control
0xE
8
read-write
n
0x0
0x0
DQOS
Data Transfer Quality of Service
4
2
DQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
FQOS
Fetch Quality of Service
2
2
FQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
WRBQOS
Write-Back Quality of Service
0
2
WRBQOSSelect
DISABLE
Background (no sensitive operation)
0x0
LOW
Sensitive Bandwidth
0x1
MEDIUM
Sensitive Latency
0x2
HIGH
Critical Latency
0x3
SWTRIGCTRL
Software Trigger Control
0x10
32
read-write
n
0x0
0x0
SWTRIG0
Channel 0 Software Trigger
0
1
SWTRIG1
Channel 1 Software Trigger
1
1
SWTRIG2
Channel 2 Software Trigger
2
1
SWTRIG3
Channel 3 Software Trigger
3
1
SWTRIG4
Channel 4 Software Trigger
4
1
SWTRIG5
Channel 5 Software Trigger
5
1
SWTRIG6
Channel 6 Software Trigger
6
1
SWTRIG7
Channel 7 Software Trigger
7
1
WRBADDR
Write-Back Memory Section Base Address
0x38
32
read-write
n
0x0
0x0
WRBADDR
Write-Back Memory Base Address
0
32
DSU
Device Service Unit
DSU
0x0
0x0
0x2000
registers
n
ADDR
Address
0x4
32
read-write
n
0x0
0x0
ADDR
Address
2
30
AMOD
Access Mode
0
2
BCC0
Boot ROM Communication Channel n
0x20
32
read-write
n
0x0
0x0
DATA
Data
0
32
BCC1
Boot ROM Communication Channel n
0x24
32
read-write
n
0x0
0x0
DATA
Data
0
32
CFG
Configuration
0x1C
32
read-write
n
0x0
0x0
DCCDMALEVEL
DMA Trigger Level
2
2
DCCDMALEVELSelect
EMPTY
Trigger rises when DCC is empty
0
FULL
Trigger rises when DCC is full
1
LQOS
Latency Quality Of Service
0
2
CID0
Component Identification 0
0x1FF0
32
read-only
n
0x0
0x0
PREAMBLEB0
Preamble Byte 0
0
8
CID1
Component Identification 1
0x1FF4
32
read-only
n
0x0
0x0
CCLASS
Component Class
4
4
PREAMBLE
Preamble
0
4
CID2
Component Identification 2
0x1FF8
32
read-only
n
0x0
0x0
PREAMBLEB2
Preamble Byte 2
0
8
CID3
Component Identification 3
0x1FFC
32
read-only
n
0x0
0x0
PREAMBLEB3
Preamble Byte 3
0
8
CTRL
Control
0x0
8
write-only
n
0x0
0x0
CRC
32-bit Cyclic Redundancy Code
2
1
MBIST
Memory built-in self-test
3
1
SWRST
Software Reset
0
1
DATA
Data
0xC
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCC0
Debug Communication Channel n
0x10
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCC1
Debug Communication Channel n
0x14
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCFG0
Device Configuration
0xF0
32
read-write
n
0x0
0x0
DCFG
Device Configuration
0
32
DCFG1
Device Configuration
0xF4
32
read-write
n
0x0
0x0
DCFG
Device Configuration
0
32
DID
Device Identification
0x18
32
read-only
n
0x0
0x0
DEVSEL
Device Select
0
8
DIE
Die Number
12
4
FAMILY
Family
23
5
FAMILYSelect
0
General purpose microcontroller
0
1
PicoPower
1
PROCESSOR
Processor
28
4
PROCESSORSelect
CM0P
Cortex-M0+
0x1
CM23
Cortex-M23
0x2
CM3
Cortex-M3
0x3
CM4
Cortex-M4
0x5
CM4F
Cortex-M4 with FPU
0x6
CM33
Cortex-M33
0x7
REVISION
Revision Number
8
4
SERIES
Series
16
6
SERIESSelect
0
Cortex-M0+ processor, basic feature set
0
1
Cortex-M0+ processor, USB
1
3
SAM L11
3
4
SAM L10
4
END
CoreSight ROM Table End
0x1008
32
read-only
n
0x0
0x0
END
End Marker
0
32
ENTRY0
CoreSight ROM Table Entry 0
0x1000
32
read-only
n
0x0
0x0
ADDOFF
Address Offset
12
20
EPRES
Entry Present
0
1
FMT
Format
1
1
ENTRY1
CoreSight ROM Table Entry 1
0x1004
32
read-only
n
0x0
0x0
ADDOFF
Address Offset
12
20
EPRES
Entry Present
0
1
FMT
Format
1
1
LENGTH
Length
0x8
32
read-write
n
0x0
0x0
LENGTH
Length
2
30
MEMTYPE
CoreSight ROM Table Memory Type
0x1FCC
32
read-only
n
0x0
0x0
SMEMP
System Memory Present
0
1
PID0
Peripheral Identification 0
0x1FE0
32
read-only
n
0x0
0x0
PARTNBL
Part Number Low
0
8
PID1
Peripheral Identification 1
0x1FE4
32
read-only
n
0x0
0x0
JEPIDCL
Low part of the JEP-106 Identity Code
4
4
PARTNBH
Part Number High
0
4
PID2
Peripheral Identification 2
0x1FE8
32
read-only
n
0x0
0x0
JEPIDCH
JEP-106 Identity Code High
0
3
JEPU
JEP-106 Identity Code is used
3
1
REVISION
Revision Number
4
4
PID3
Peripheral Identification 3
0x1FEC
32
read-only
n
0x0
0x0
CUSMOD
ARM CUSMOD
0
4
REVAND
Revision Number
4
4
PID4
Peripheral Identification 4
0x1FD0
32
read-only
n
0x0
0x0
FKBC
4KB count
4
4
JEPCC
JEP-106 Continuation Code
0
4
PID5
Peripheral Identification 5
0x1FD4
32
read-only
n
0x0
0x0
PID6
Peripheral Identification 6
0x1FD8
32
read-only
n
0x0
0x0
PID7
Peripheral Identification 7
0x1FDC
32
read-only
n
0x0
0x0
STATUSA
Status A
0x1
8
read-write
n
0x0
0x0
BERR
Bus Error
2
1
BREXT
BootRom Phase Extension
5
1
CRSTEXT
CPU Reset Phase Extension
1
1
DONE
Done
0
1
FAIL
Failure
3
1
PERR
Protection Error Detected by the State Machine
4
1
STATUSB
Status B
0x2
8
read-only
n
0x0
0x0
BCCD0
Boot ROM Communication Channel 0 Dirty
6
1
BCCD1
Boot ROM Communication Channel 1 Dirty
7
1
DAL
Debugger Access Level
0
2
DALSelect
SECURED
0x0
NS_DEBUG
0x1
FULL_DEBUG
0x2
DBGPRES
Debugger Present
2
1
DCCD0
Debug Communication Channel 0 Dirty
4
1
DCCD1
Debug Communication Channel 1 Dirty
5
1
HPE
Hot-Plugging Enable
3
1
STATUSC
Status C
0x3
8
read-only
n
0x0
0x0
DSU_EXT
Device Service Unit
DSU
0x0
0x0
0x2000
registers
n
ADDR
Address
0x4
32
read-write
n
0x0
0x0
ADDR
Address
2
30
AMOD
Access Mode
0
2
BCC0
Boot ROM Communication Channel n
0x20
32
read-write
n
0x0
0x0
DATA
Data
0
32
BCC1
Boot ROM Communication Channel n
0x24
32
read-write
n
0x0
0x0
DATA
Data
0
32
CFG
Configuration
0x1C
32
read-write
n
0x0
0x0
DCCDMALEVEL
DMA Trigger Level
2
2
DCCDMALEVELSelect
EMPTY
Trigger rises when DCC is empty
0
FULL
Trigger rises when DCC is full
1
LQOS
Latency Quality Of Service
0
2
CID0
Component Identification 0
0x1FF0
32
read-only
n
0x0
0x0
PREAMBLEB0
Preamble Byte 0
0
8
CID1
Component Identification 1
0x1FF4
32
read-only
n
0x0
0x0
CCLASS
Component Class
4
4
PREAMBLE
Preamble
0
4
CID2
Component Identification 2
0x1FF8
32
read-only
n
0x0
0x0
PREAMBLEB2
Preamble Byte 2
0
8
CID3
Component Identification 3
0x1FFC
32
read-only
n
0x0
0x0
PREAMBLEB3
Preamble Byte 3
0
8
CTRL
Control
0x0
8
write-only
n
0x0
0x0
CRC
32-bit Cyclic Redundancy Code
2
1
MBIST
Memory built-in self-test
3
1
SWRST
Software Reset
0
1
DATA
Data
0xC
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCC0
Debug Communication Channel n
0x10
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCC1
Debug Communication Channel n
0x14
32
read-write
n
0x0
0x0
DATA
Data
0
32
DCFG0
Device Configuration
0xF0
32
read-write
n
0x0
0x0
DCFG
Device Configuration
0
32
DCFG1
Device Configuration
0xF4
32
read-write
n
0x0
0x0
DCFG
Device Configuration
0
32
DID
Device Identification
0x18
32
read-only
n
0x0
0x0
DEVSEL
Device Select
0
8
DIE
Die Number
12
4
FAMILY
Family
23
5
FAMILYSelect
0
General purpose microcontroller
0
1
PicoPower
1
PROCESSOR
Processor
28
4
PROCESSORSelect
CM0P
Cortex-M0+
0x1
CM23
Cortex-M23
0x2
CM3
Cortex-M3
0x3
CM4
Cortex-M4
0x5
CM4F
Cortex-M4 with FPU
0x6
CM33
Cortex-M33
0x7
REVISION
Revision Number
8
4
SERIES
Series
16
6
SERIESSelect
0
Cortex-M0+ processor, basic feature set
0
1
Cortex-M0+ processor, USB
1
3
SAM L11
3
4
SAM L10
4
END
CoreSight ROM Table End
0x1008
32
read-only
n
0x0
0x0
END
End Marker
0
32
ENTRY0
CoreSight ROM Table Entry 0
0x1000
32
read-only
n
0x0
0x0
ADDOFF
Address Offset
12
20
EPRES
Entry Present
0
1
FMT
Format
1
1
ENTRY1
CoreSight ROM Table Entry 1
0x1004
32
read-only
n
0x0
0x0
ADDOFF
Address Offset
12
20
EPRES
Entry Present
0
1
FMT
Format
1
1
LENGTH
Length
0x8
32
read-write
n
0x0
0x0
LENGTH
Length
2
30
MEMTYPE
CoreSight ROM Table Memory Type
0x1FCC
32
read-only
n
0x0
0x0
SMEMP
System Memory Present
0
1
PID0
Peripheral Identification 0
0x1FE0
32
read-only
n
0x0
0x0
PARTNBL
Part Number Low
0
8
PID1
Peripheral Identification 1
0x1FE4
32
read-only
n
0x0
0x0
JEPIDCL
Low part of the JEP-106 Identity Code
4
4
PARTNBH
Part Number High
0
4
PID2
Peripheral Identification 2
0x1FE8
32
read-only
n
0x0
0x0
JEPIDCH
JEP-106 Identity Code High
0
3
JEPU
JEP-106 Identity Code is used
3
1
REVISION
Revision Number
4
4
PID3
Peripheral Identification 3
0x1FEC
32
read-only
n
0x0
0x0
CUSMOD
ARM CUSMOD
0
4
REVAND
Revision Number
4
4
PID4
Peripheral Identification 4
0x1FD0
32
read-only
n
0x0
0x0
FKBC
4KB count
4
4
JEPCC
JEP-106 Continuation Code
0
4
PID5
Peripheral Identification 5
0x1FD4
32
read-only
n
0x0
0x0
PID6
Peripheral Identification 6
0x1FD8
32
read-only
n
0x0
0x0
PID7
Peripheral Identification 7
0x1FDC
32
read-only
n
0x0
0x0
STATUSA
Status A
0x1
8
read-write
n
0x0
0x0
BERR
Bus Error
2
1
BREXT
BootRom Phase Extension
5
1
CRSTEXT
CPU Reset Phase Extension
1
1
DONE
Done
0
1
FAIL
Failure
3
1
PERR
Protection Error Detected by the State Machine
4
1
STATUSB
Status B
0x2
8
read-only
n
0x0
0x0
BCCD0
Boot ROM Communication Channel 0 Dirty
6
1
BCCD1
Boot ROM Communication Channel 1 Dirty
7
1
DAL
Debugger Access Level
0
2
DALSelect
SECURED
0x0
NS_DEBUG
0x1
FULL_DEBUG
0x2
DBGPRES
Debugger Present
2
1
DCCD0
Debug Communication Channel 0 Dirty
4
1
DCCD1
Debug Communication Channel 1 Dirty
5
1
HPE
Hot-Plugging Enable
3
1
STATUSC
Status C
0x3
8
read-only
n
0x0
0x0
DWT
Data Watchpoint and Trace
DWT
0x0
0x0
0x1000
registers
n
CIDR0
DWT Component Identification Register 0
0xFF0
32
read-only
n
0x0
0x0
PRMBL_0
CoreSight component identification preamble
0
8
CIDR1
DWT Component Identification Register 1
0xFF4
32
read-only
n
0x0
0x0
CLASS
CoreSight component class
4
4
PRMBL_1
CoreSight component identification preamble
0
4
CIDR2
DWT Component Identification Register 2
0xFF8
32
read-only
n
0x0
0x0
PRMBL_2
CoreSight component identification preamble
0
8
CIDR3
DWT Component Identification Register 3
0xFFC
32
read-only
n
0x0
0x0
PRMBL_3
CoreSight component identification preamble
0
8
COMP
DWT Comparator Register n
0x0
32
read-write
n
0x0
0x0
VALUE
Cycle/PC/data value or data address
0
32
CTRL
DWT Control Register
0x0
32
read-write
n
0x0
0x0
CPIEVTENA
CPI event enable
17
1
CYCCNTENA
CYCCNT enable
0
1
CYCDISS
Cycle counter disabled secure
23
1
CYCEVTENA
Cycle event enable
22
1
CYCTAP
Cycle count tap
9
1
EXCEVTENA
Exception event enable
18
1
EXCTRCENA
Exception trace enable
16
1
FOLDEVTENA
Fold event enable
21
1
LSUEVTENA
LSU event enable
20
1
NOCYCCNT
No cycle count
25
1
NOEXTTRIG
No external triggers
26
1
NOPRFCNT
No profile counters
24
1
NOTRCPKT
No trace packets
27
1
NUMCOMP
Number of comparators
28
4
PCSAMPLENA
PC sample enable
12
1
POSTINIT
POSTCNT initial
5
4
POSTPRESET
POSTCNT preset
1
4
SLEEPEVTENA
Sleep event enable
19
1
SYNCTAP
Synchronization tap
10
2
DEVARCH
DWT Device Architecture Register
0xFBC
32
read-only
n
0x0
0x0
ARCHITECT
Architect
21
11
ARCHPART
Architecture Part
0
12
ARCHVER
Architecture Version
12
4
PRESENT
DEVARCH Present
20
1
REVISION
Revision
16
4
DEVTYPE
DWT Device Type Register
0xFCC
32
read-only
n
0x0
0x0
MAJOR
Major type
0
4
SUB
Sub-type
4
4
FUNCTION
DWT Function Register x
0x8
32
read-write
n
0x0
0x0
ACTION
Action on match
4
2
DATAVSIZE
Data value size
10
2
ID
Identify capability
27
5
MATCH
Match type
0
4
MATCHED
Comparator matched
24
1
LAR
DWT Software Lock Access Register
0xFB0
32
write-only
n
0x0
0x0
KEY
Lock access control
0
32
KEYSelect
UNLOCK
Unlock key value
0xC5ACCE55
LSR
DWT Software Lock Status Register
0xFB4
32
read-only
n
0x0
0x0
nTT
Not thirty-two bit
2
1
SLI
Software Lock implemented
0
1
SLK
Software Lock status
1
1
PCSR
DWT Program Counter Sample Register
0x1C
32
read-only
n
0x0
0x0
EIASAMPLE
Executed instruction address sample
0
32
PIDR0
DWT Peripheral Identification Register 0
0xFE0
32
read-only
n
0x0
0x0
PART_0
Part number bits[7:0]
0
8
PIDR1
DWT Peripheral Identification Register 1
0xFE4
32
read-only
n
0x0
0x0
DES_0
JEP106 identification code bits [3:0]
4
4
PART_1
Part number bits[11:8]
0
4
PIDR2
DWT Peripheral Identification Register 2
0xFE8
32
read-only
n
0x0
0x0
DES_1
JEP106 identification code bits[6:4]
0
3
JEDEC
JEDEC assignee value is used
3
1
REVISION
Component revision
4
4
PIDR3
DWT Peripheral Identification Register 3
0xFEC
32
read-only
n
0x0
0x0
CMOD
Customer Modified
0
4
REVAND
RevAnd
4
4
PIDR4
DWT Peripheral Identification Register 4
0xFD0
32
read-only
n
0x0
0x0
DES_2
JEP106 continuation code
0
4
SIZE
4KB count
4
4
PIDR5
DWT Peripheral Identification Register 5
0xFD4
32
read-only
n
0x0
0x0
PIDR6
DWT Peripheral Identification Register 6
0xFD8
32
read-only
n
0x0
0x0
PIDR7
DWT Peripheral Identification Register 7
0xFDC
32
read-only
n
0x0
0x0
EIC
External Interrupt Controller
EIC
0x0
0x0
0x44
registers
n
EIC_0
3
EIC_EXTINT_0
3
EIC_1
4
EIC_EXTINT_1
4
EIC_2
5
EIC_EXTINT_2
5
EIC_3
6
EIC_EXTINT_3
6
EIC_OTHER
7
ASYNCH
External Interrupt Asynchronous Mode
0x18
32
read-write
n
0x0
0x0
ASYNCH
Asynchronous Edge Detection Mode
0
8
ASYNCHSelect
SYNC
Edge detection is clock synchronously operated
0
ASYNC
Edge detection is clock asynchronously operated
1
CONFIG
External Interrupt Sense Configuration
0x1C
32
read-write
n
0x0
0x0
FILTEN0
Filter Enable 0
3
1
FILTEN1
Filter Enable 1
7
1
FILTEN2
Filter Enable 2
11
1
FILTEN3
Filter Enable 3
15
1
FILTEN4
Filter Enable 4
19
1
FILTEN5
Filter Enable 5
23
1
FILTEN6
Filter Enable 6
27
1
FILTEN7
Filter Enable 7
31
1
SENSE0
Input Sense Configuration 0
0
3
SENSE0Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE1
Input Sense Configuration 1
4
3
SENSE1Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE2
Input Sense Configuration 2
8
3
SENSE2Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE3
Input Sense Configuration 3
12
3
SENSE3Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE4
Input Sense Configuration 4
16
3
SENSE4Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE5
Input Sense Configuration 5
20
3
SENSE5Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE6
Input Sense Configuration 6
24
3
SENSE6Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE7
Input Sense Configuration 7
28
3
SENSE7Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
CONFIG1
External Interrupt Sense Configuration
0x1C
32
read-write
n
0x0
0x0
FILTEN0
Filter Enable 0
3
1
FILTEN1
Filter Enable 1
7
1
FILTEN2
Filter Enable 2
11
1
FILTEN3
Filter Enable 3
15
1
FILTEN4
Filter Enable 4
19
1
FILTEN5
Filter Enable 5
23
1
FILTEN6
Filter Enable 6
27
1
FILTEN7
Filter Enable 7
31
1
SENSE0
Input Sense Configuration 0
0
3
SENSE0Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE1
Input Sense Configuration 1
4
3
SENSE1Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE2
Input Sense Configuration 2
8
3
SENSE2Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE3
Input Sense Configuration 3
12
3
SENSE3Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE4
Input Sense Configuration 4
16
3
SENSE4Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE5
Input Sense Configuration 5
20
3
SENSE5Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE6
Input Sense Configuration 6
24
3
SENSE6Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
SENSE7
Input Sense Configuration 7
28
3
SENSE7Select
NONE
No detection
0
RISE
Rising edge detection
1
FALL
Falling edge detection
2
BOTH
Both edges detection
3
HIGH
High level detection
4
LOW
Low level detection
5
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
CKSEL
Clock Selection
4
1
CKSELSelect
CLK_GCLK
Clocked by GCLK
0
CLK_ULP32K
Clocked by ULP32K
1
ENABLE
Enable
1
1
SWRST
Software Reset
0
1
DEBOUNCEN
Debouncer Enable
0x30
32
read-write
n
0x0
0x0
DEBOUNCEN
Debouncer Enable
0
8
DPRESCALER
Debouncer Prescaler
0x34
32
read-write
n
0x0
0x0
PRESCALER0
Debouncer Prescaler
0
3
PRESCALER0Select
DIV2
EIC clock divided by 2
0
DIV4
EIC clock divided by 4
1
DIV8
EIC clock divided by 8
2
DIV16
EIC clock divided by 16
3
DIV32
EIC clock divided by 32
4
DIV64
EIC clock divided by 64
5
DIV128
EIC clock divided by 128
6
DIV256
EIC clock divided by 256
7
STATES0
Debouncer number of states
3
1
TICKON
Pin Sampler frequency selection
16
1
EVCTRL
Event Control
0x8
32
read-write
n
0x0
0x0
EXTINTEO
External Interrupt Event Output Enable
0
8
INTENCLR
Interrupt Enable Clear
0xC
32
read-write
n
0x0
0x0
EXTINT
External Interrupt Enable
0
8
NSCHK
Non-secure Check Interrupt Enable
31
1
INTENSET
Interrupt Enable Set
0x10
32
read-write
n
0x0
0x0
EXTINT
External Interrupt Enable
0
8
NSCHK
Non-secure Check Interrupt Enable
31
1
INTFLAG
Interrupt Flag Status and Clear
0x14
32
read-write
n
0x0
0x0
EXTINT
External Interrupt
0
8
NSCHK
Non-secure Check Interrupt
31
1
NMICTRL
Non-Maskable Interrupt Control
0x1
8
read-write
n
0x0
0x0
NMIASYNCH
Asynchronous Edge Detection Mode
4
1
NMIASYNCHSelect
SYNC
Edge detection is clock synchronously operated
0
ASYNC
Edge detection is clock asynchronously operated
1
NMIFILTEN
Non-Maskable Interrupt Filter Enable
3
1
NMISENSE
Non-Maskable Interrupt Sense Configuration
0
3
NMISENSESelect
NONE
No detection
0
RISE
Rising-edge detection
1
FALL
Falling-edge detection
2
BOTH
Both-edges detection
3
HIGH
High-level detection
4
LOW
Low-level detection
5
NMIFLAG
Non-Maskable Interrupt Flag Status and Clear
0x2
8
read-write
n
0x0
0x0
NMI
Non-Maskable Interrupt
0
1
NONSEC
Non-secure Interrupt
0x40
32
read-write
n
0x0
0x0
EXTINT
External Interrupt Nonsecure Enable
0
8
NMI
Non-Maskable Interrupt Nonsecure Enable
31
1
NSCHK
Non-secure Interrupt Check Enable
0x3C
32
read-write
n
0x0
0x0
EXTINT
External Interrupt Nonsecure Check Enable
0
8
NMI
Non-Maskable External Interrupt Nonsecure Check Enable
31
1
PINSTATE
Pin State
0x38
32
read-only
n
0x0
0x0
PINSTATE
Pin State
0
8
SYNCBUSY
Synchronization Busy
0x4
32
read-only
n
0x0
0x0
ENABLE
Enable Synchronization Busy Status
1
1
SWRST
Software Reset Synchronization Busy Status
0
1
EVSYS
Event System Interface
EVSYS
0x0
0x0
0x1F4
registers
n
EVSYS_0
16
EVSYS_1
17
EVSYS_2
18
EVSYS_3
19
EVSYS_NSCHK
20
BUSYCH
Busy Channels
0x18
32
read-only
n
0x0
0x0
BUSYCH0
Busy Channel 0
0
1
BUSYCH1
Busy Channel 1
1
1
BUSYCH2
Busy Channel 2
2
1
BUSYCH3
Busy Channel 3
3
1
CHANNEL
Channel n Control
0x0
32
read-write
n
0x0
0x0
EDGSEL
Edge Detection Selection
10
2
EDGSELSelect
NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
0
RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
1
FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
2
BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
3
EVGEN
Event Generator Selection
0
6
ONDEMAND
Generic Clock On Demand
15
1
PATH
Path Selection
8
2
PATHSelect
SYNCHRONOUS
Synchronous path
0
RESYNCHRONIZED
Resynchronized path
1
ASYNCHRONOUS
Asynchronous path
2
RUNSTDBY
Run in standby
14
1
CHINTENCLR
Channel n Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
EVD
Channel Event Detected Interrupt Disable
1
1
OVR
Channel Overrun Interrupt Disable
0
1
CHINTENSET
Channel n Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
EVD
Channel Event Detected Interrupt Enable
1
1
OVR
Channel Overrun Interrupt Enable
0
1
CHINTFLAG
Channel n Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
EVD
Channel Event Detected
1
1
OVR
Channel Overrun
0
1
CHSTATUS
Channel n Status
0x7
8
read-only
n
0x0
0x0
BUSYCH
Busy Channel
1
1
RDYUSR
Ready User
0
1
CTRLA
Control
0x0
8
write-only
n
0x0
0x0
SWRST
Software Reset
0
1
INTENCLR
Interrupt Enable Clear
0x1D4
8
read-write
n
0x0
0x0
NSCHK
Non-Secure Check Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x1D5
8
read-write
n
0x0
0x0
NSCHK
Non-Secure Check Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x1D6
8
read-write
n
0x0
0x0
NSCHK
Non-Secure Check
0
1
INTPEND
Channel Pending Interrupt
0x10
16
read-write
n
0x0
0x0
BUSY
Busy
15
1
EVD
Channel Event Detected
9
1
ID
Channel ID
0
2
OVR
Channel Overrun
8
1
READY
Ready
14
1
INTSTATUS
Interrupt Status
0x14
32
read-only
n
0x0
0x0
CHINT0
Channel 0 Pending Interrupt
0
1
CHINT1
Channel 1 Pending Interrupt
1
1
CHINT2
Channel 2 Pending Interrupt
2
1
CHINT3
Channel 3 Pending Interrupt
3
1
NONSECCHAN
Channels Security Attribution
0x1D8
32
read-write
n
0x0
0x0
CHANNEL0
Non-Secure for Channel 0
0
1
CHANNEL1
Non-Secure for Channel 1
1
1
CHANNEL2
Non-Secure for Channel 2
2
1
CHANNEL3
Non-Secure for Channel 3
3
1
CHANNEL4
Non-Secure for Channel 4
4
1
CHANNEL5
Non-Secure for Channel 5
5
1
CHANNEL6
Non-Secure for Channel 6
6
1
CHANNEL7
Non-Secure for Channel 7
7
1
NONSECUSER1
Users Security Attribution
0x1E0
32
read-write
n
0x0
0x0
USER0
Non-Secure for User 0
0
1
USER1
Non-Secure for User 1
1
1
USER10
Non-Secure for User 10
10
1
USER11
Non-Secure for User 11
11
1
USER12
Non-Secure for User 12
12
1
USER13
Non-Secure for User 13
13
1
USER14
Non-Secure for User 14
14
1
USER15
Non-Secure for User 15
15
1
USER16
Non-Secure for User 16
16
1
USER17
Non-Secure for User 17
17
1
USER18
Non-Secure for User 18
18
1
USER19
Non-Secure for User 19
19
1
USER2
Non-Secure for User 2
2
1
USER20
Non-Secure for User 20
20
1
USER21
Non-Secure for User 21
21
1
USER22
Non-Secure for User 22
22
1
USER3
Non-Secure for User 3
3
1
USER4
Non-Secure for User 4
4
1
USER5
Non-Secure for User 5
5
1
USER6
Non-Secure for User 6
6
1
USER7
Non-Secure for User 7
7
1
USER8
Non-Secure for User 8
8
1
USER9
Non-Secure for User 9
9
1
NSCHKCHAN
Non-Secure Channels Check
0x1DC
32
read-write
n
0x0
0x0
CHANNEL0
Channel 0 to be checked as non-secured
0
1
CHANNEL1
Channel 1 to be checked as non-secured
1
1
CHANNEL2
Channel 2 to be checked as non-secured
2
1
CHANNEL3
Channel 3 to be checked as non-secured
3
1
CHANNEL4
Channel 4 to be checked as non-secured
4
1
CHANNEL5
Channel 5 to be checked as non-secured
5
1
CHANNEL6
Channel 6 to be checked as non-secured
6
1
CHANNEL7
Channel 7 to be checked as non-secured
7
1
NSCHKUSER1
Non-Secure Users Check
0x1F0
32
read-write
n
0x0
0x0
USER0
User 0 to be checked as non-secured
0
1
USER1
User 1 to be checked as non-secured
1
1
USER10
User 10 to be checked as non-secured
10
1
USER11
User 11 to be checked as non-secured
11
1
USER12
User 12 to be checked as non-secured
12
1
USER13
User 13 to be checked as non-secured
13
1
USER14
User 14 to be checked as non-secured
14
1
USER15
User 15 to be checked as non-secured
15
1
USER16
User 16 to be checked as non-secured
16
1
USER17
User 17 to be checked as non-secured
17
1
USER18
User 18 to be checked as non-secured
18
1
USER19
User 19 to be checked as non-secured
19
1
USER2
User 2 to be checked as non-secured
2
1
USER20
User 20 to be checked as non-secured
20
1
USER21
User 21 to be checked as non-secured
21
1
USER22
User 22 to be checked as non-secured
22
1
USER3
User 3 to be checked as non-secured
3
1
USER4
User 4 to be checked as non-secured
4
1
USER5
User 5 to be checked as non-secured
5
1
USER6
User 6 to be checked as non-secured
6
1
USER7
User 7 to be checked as non-secured
7
1
USER8
User 8 to be checked as non-secured
8
1
USER9
User 9 to be checked as non-secured
9
1
PRICTRL
Priority Control
0x8
8
read-write
n
0x0
0x0
PRI
Channel Priority Number
0
2
RREN
Round-Robin Scheduling Enable
7
1
READYUSR
Ready Users
0x1C
32
read-only
n
0x0
0x0
READYUSR0
Ready User for Channel 0
0
1
READYUSR1
Ready User for Channel 1
1
1
READYUSR2
Ready User for Channel 2
2
1
READYUSR3
Ready User for Channel 3
3
1
SWEVT
Software Event
0x4
32
write-only
n
0x0
0x0
CHANNEL0
Channel 0 Software Selection
0
1
CHANNEL1
Channel 1 Software Selection
1
1
CHANNEL2
Channel 2 Software Selection
2
1
CHANNEL3
Channel 3 Software Selection
3
1
CHANNEL4
Channel 4 Software Selection
4
1
CHANNEL5
Channel 5 Software Selection
5
1
CHANNEL6
Channel 6 Software Selection
6
1
CHANNEL7
Channel 7 Software Selection
7
1
USER0
User Multiplexer n
0x120
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER1
User Multiplexer n
0x121
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER10
User Multiplexer n
0x12A
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER11
User Multiplexer n
0x12B
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER12
User Multiplexer n
0x12C
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER13
User Multiplexer n
0x12D
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER14
User Multiplexer n
0x12E
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER15
User Multiplexer n
0x12F
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER16
User Multiplexer n
0x130
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER17
User Multiplexer n
0x131
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER18
User Multiplexer n
0x132
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER19
User Multiplexer n
0x133
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER2
User Multiplexer n
0x122
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER20
User Multiplexer n
0x134
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER21
User Multiplexer n
0x135
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER22
User Multiplexer n
0x136
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER3
User Multiplexer n
0x123
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER4
User Multiplexer n
0x124
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER5
User Multiplexer n
0x125
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER6
User Multiplexer n
0x126
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER7
User Multiplexer n
0x127
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER8
User Multiplexer n
0x128
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
USER9
User Multiplexer n
0x129
8
read-write
n
0x0
0x0
CHANNEL
Channel Event Selection
0
4
FPB
Flash Patch and Breakpoint
FPB
0x0
0x0
0x1000
registers
n
FP_CIDR0
FP Component Identification Register 0
0xFF0
32
read-only
n
0x0
0x0
PRMBL_0
CoreSight component identification preamble
0
8
FP_CIDR1
FP Component Identification Register 1
0xFF4
32
read-only
n
0x0
0x0
CLASS
CoreSight component class
4
4
PRMBL_1
CoreSight component identification preamble
0
4
FP_CIDR2
FP Component Identification Register 2
0xFF8
32
read-only
n
0x0
0x0
PRMBL_2
CoreSight component identification preamble
0
8
FP_CIDR3
FP Component Identification Register 3
0xFFC
32
read-only
n
0x0
0x0
PRMBL_3
CoreSight component identification preamble
0
8
FP_COMP0
Flash Patch Comparator Register n
0x8
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
FE
Flash Patch enable
31
1
FPADDR
Flash Patch address
2
27
FP_COMP1
Flash Patch Comparator Register n
0xC
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
FE
Flash Patch enable
31
1
FPADDR
Flash Patch address
2
27
FP_COMP2
Flash Patch Comparator Register n
0x10
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
FE
Flash Patch enable
31
1
FPADDR
Flash Patch address
2
27
FP_COMP3
Flash Patch Comparator Register n
0x14
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
FE
Flash Patch enable
31
1
FPADDR
Flash Patch address
2
27
FP_COMP_BREAKPOINT_MODE0
Flash Patch Comparator Register n
FP_COMP[%s]
0x8
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
BPADDR
Breakpoint address
1
31
FP_COMP_BREAKPOINT_MODE1
Flash Patch Comparator Register n
FP_COMP[%s]
0xC
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
BPADDR
Breakpoint address
1
31
FP_COMP_BREAKPOINT_MODE2
Flash Patch Comparator Register n
FP_COMP[%s]
0x10
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
BPADDR
Breakpoint address
1
31
FP_COMP_BREAKPOINT_MODE3
Flash Patch Comparator Register n
FP_COMP[%s]
0x14
32
read-write
n
0x0
0x0
BE
Breakpoint enable
0
1
BPADDR
Breakpoint address
1
31
FP_CTRL
Flash Patch Control Register
0x0
32
read-write
n
0x0
0x0
ENABLE
Flash Patch global enable
0
1
KEY
FP_CTRL write-enable key
1
1
NUM_CODE
Number of implemented code comparators bits [3:0]
4
4
NUM_CODE_1
Number of implemented code comparators bits [6:4]
12
3
NUM_LIT
Number of literal comparators
8
4
REV
Revision
28
4
FP_DEVARCH
FPB Device Architecture Register
0xFBC
32
read-only
n
0x0
0x0
ARCHITECT
Architect
21
11
ARCHPART
Architecture Part
0
12
ARCHVER
Architecture Version
12
4
PRESENT
DEVARCH Present
20
1
REVISION
Revision
16
4
FP_DEVTYPE
FPB Device Type Register
0xFCC
32
read-only
n
0x0
0x0
MAJOR
Major type
0
4
SUB
Sub-type
4
4
FP_LAR
FPB Software Lock Access Register
0xFB0
32
write-only
n
0x0
0x0
KEY
Lock access control
0
32
KEYSelect
UNLOCK
Unlock key value
0xC5ACCE55
FP_LSR
FPB Software Lock Status Register
0xFB4
32
read-only
n
0x0
0x0
nTT
Not thirty-two bit
2
1
SLI
Software Lock implemented
0
1
SLK
Software Lock status
1
1
FP_PIDR0
FP Peripheral Identification Register 0
0xFE0
32
read-only
n
0x0
0x0
PART_0
Part number bits[7:0]
0
8
FP_PIDR1
FP Peripheral Identification Register 1
0xFE4
32
read-only
n
0x0
0x0
DES_0
JEP106 identification code bits [3:0]
4
4
PART_1
Part number bits[11:8]
0
4
FP_PIDR2
FP Peripheral Identification Register 2
0xFE8
32
read-only
n
0x0
0x0
DES_1
JEP106 identification code bits[6:4]
0
3
JEDEC
JEDEC assignee value is used
3
1
REVISION
Component revision
4
4
FP_PIDR3
FP Peripheral Identification Register 3
0xFEC
32
read-only
n
0x0
0x0
CMOD
Customer Modified
0
4
REVAND
RevAnd
4
4
FP_PIDR4
FP Peripheral Identification Register 4
0xFD0
32
read-only
n
0x0
0x0
DES_2
JEP106 continuation code
0
4
SIZE
4KB count
4
4
FP_PIDR5
FP Peripheral Identification Register 5
0xFD4
32
read-only
n
0x0
0x0
FP_PIDR6
FP Peripheral Identification Register 6
0xFD8
32
read-only
n
0x0
0x0
FP_PIDR7
FP Peripheral Identification Register 7
0xFDC
32
read-only
n
0x0
0x0
FP_REMAP
Flash Patch Remap Register
0x4
32
read-only
n
0x0
0x0
REMAP
Remap address
5
24
RMPSPT
Remap supported
29
1
FREQM
Frequency Meter
FREQM
0x0
0x0
0x14
registers
n
FREQM
8
CFGA
Config A register
0x2
16
read-write
n
0x0
0x0
DIVREF
Divide Reference Clock
15
1
REFNUM
Number of Reference Clock Cycles
0
8
CTRLA
Control A Register
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
SWRST
Software Reset
0
1
CTRLB
Control B Register
0x1
8
write-only
n
0x0
0x0
START
Start Measurement
0
1
INTENCLR
Interrupt Enable Clear Register
0x8
8
read-write
n
0x0
0x0
DONE
Measurement Done Interrupt Enable
0
1
INTENSET
Interrupt Enable Set Register
0x9
8
read-write
n
0x0
0x0
DONE
Measurement Done Interrupt Enable
0
1
INTFLAG
Interrupt Flag Register
0xA
8
read-write
n
0x0
0x0
DONE
Measurement Done
0
1
STATUS
Status Register
0xB
8
read-write
n
0x0
0x0
BUSY
FREQM Status
0
1
OVF
Sticky Count Value Overflow
1
1
SYNCBUSY
Synchronization Busy Register
0xC
32
read-only
n
0x0
0x0
ENABLE
Enable
1
1
SWRST
Software Reset
0
1
VALUE
Count Value Register
0x10
32
read-only
n
0x0
0x0
VALUE
Measurement Value
0
24
GCLK
Generic Clock Generator
GCLK
0x0
0x0
0x104
registers
n
CTRLA
Control
0x0
8
read-write
n
0x0
0x0
SWRST
Software Reset
0
1
GENCTRL0
Generic Clock Generator Control
0x20
32
read-write
n
0x0
0x0
DIV
Division Factor
16
16
DIVSEL
Divide Selection
12
1
DIVSELSelect
DIV1
Divide input directly by divider factor
0x0
DIV2
Divide input by 2^(divider factor+ 1)
0x1
GENEN
Generic Clock Generator Enable
8
1
IDC
Improve Duty Cycle
9
1
OE
Output Enable
11
1
OOV
Output Off Value
10
1
RUNSTDBY
Run in Standby
13
1
SRC
Source Select
0
3
SRCSelect
XOSC
XOSC oscillator output
0
GCLKIN
Generator input pad (GCLK_IO)
1
GCLKGEN1
Generic clock generator 1 output
2
OSCULP32K
OSCULP32K oscillator output
3
XOSC32K
XOSC32K oscillator output
4
OSC16M
OSC16M oscillator output
5
DFLLULP
DFLLULP output
6
FDPLL96M
FDPLL output
7
GENCTRL1
Generic Clock Generator Control
0x24
32
read-write
n
0x0
0x0
DIV
Division Factor
16
16
DIVSEL
Divide Selection
12
1
DIVSELSelect
DIV1
Divide input directly by divider factor
0x0
DIV2
Divide input by 2^(divider factor+ 1)
0x1
GENEN
Generic Clock Generator Enable
8
1
IDC
Improve Duty Cycle
9
1
OE
Output Enable
11
1
OOV
Output Off Value
10
1
RUNSTDBY
Run in Standby
13
1
SRC
Source Select
0
3
SRCSelect
XOSC
XOSC oscillator output
0
GCLKIN
Generator input pad (GCLK_IO)
1
GCLKGEN1
Generic clock generator 1 output
2
OSCULP32K
OSCULP32K oscillator output
3
XOSC32K
XOSC32K oscillator output
4
OSC16M
OSC16M oscillator output
5
DFLLULP
DFLLULP output
6
FDPLL96M
FDPLL output
7
GENCTRL2
Generic Clock Generator Control
0x28
32
read-write
n
0x0
0x0
DIV
Division Factor
16
16
DIVSEL
Divide Selection
12
1
DIVSELSelect
DIV1
Divide input directly by divider factor
0x0
DIV2
Divide input by 2^(divider factor+ 1)
0x1
GENEN
Generic Clock Generator Enable
8
1
IDC
Improve Duty Cycle
9
1
OE
Output Enable
11
1
OOV
Output Off Value
10
1
RUNSTDBY
Run in Standby
13
1
SRC
Source Select
0
3
SRCSelect
XOSC
XOSC oscillator output
0
GCLKIN
Generator input pad (GCLK_IO)
1
GCLKGEN1
Generic clock generator 1 output
2
OSCULP32K
OSCULP32K oscillator output
3
XOSC32K
XOSC32K oscillator output
4
OSC16M
OSC16M oscillator output
5
DFLLULP
DFLLULP output
6
FDPLL96M
FDPLL output
7
GENCTRL3
Generic Clock Generator Control
0x2C
32
read-write
n
0x0
0x0
DIV
Division Factor
16
16
DIVSEL
Divide Selection
12
1
DIVSELSelect
DIV1
Divide input directly by divider factor
0x0
DIV2
Divide input by 2^(divider factor+ 1)
0x1
GENEN
Generic Clock Generator Enable
8
1
IDC
Improve Duty Cycle
9
1
OE
Output Enable
11
1
OOV
Output Off Value
10
1
RUNSTDBY
Run in Standby
13
1
SRC
Source Select
0
3
SRCSelect
XOSC
XOSC oscillator output
0
GCLKIN
Generator input pad (GCLK_IO)
1
GCLKGEN1
Generic clock generator 1 output
2
OSCULP32K
OSCULP32K oscillator output
3
XOSC32K
XOSC32K oscillator output
4
OSC16M
OSC16M oscillator output
5
DFLLULP
DFLLULP output
6
FDPLL96M
FDPLL output
7
GENCTRL4
Generic Clock Generator Control
0x30
32
read-write
n
0x0
0x0
DIV
Division Factor
16
16
DIVSEL
Divide Selection
12
1
DIVSELSelect
DIV1
Divide input directly by divider factor
0x0
DIV2
Divide input by 2^(divider factor+ 1)
0x1
GENEN
Generic Clock Generator Enable
8
1
IDC
Improve Duty Cycle
9
1
OE
Output Enable
11
1
OOV
Output Off Value
10
1
RUNSTDBY
Run in Standby
13
1
SRC
Source Select
0
3
SRCSelect
XOSC
XOSC oscillator output
0
GCLKIN
Generator input pad (GCLK_IO)
1
GCLKGEN1
Generic clock generator 1 output
2
OSCULP32K
OSCULP32K oscillator output
3
XOSC32K
XOSC32K oscillator output
4
OSC16M
OSC16M oscillator output
5
DFLLULP
DFLLULP output
6
FDPLL96M
FDPLL output
7
PCHCTRL0
Peripheral Clock Control
0x80
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL1
Peripheral Clock Control
0x84
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL10
Peripheral Clock Control
0xA8
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL11
Peripheral Clock Control
0xAC
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL12
Peripheral Clock Control
0xB0
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL13
Peripheral Clock Control
0xB4
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL14
Peripheral Clock Control
0xB8
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL15
Peripheral Clock Control
0xBC
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL16
Peripheral Clock Control
0xC0
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL17
Peripheral Clock Control
0xC4
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL18
Peripheral Clock Control
0xC8
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL19
Peripheral Clock Control
0xCC
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL2
Peripheral Clock Control
0x88
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL20
Peripheral Clock Control
0xD0
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL3
Peripheral Clock Control
0x8C
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL4
Peripheral Clock Control
0x90
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL5
Peripheral Clock Control
0x94
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL6
Peripheral Clock Control
0x98
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL7
Peripheral Clock Control
0x9C
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL8
Peripheral Clock Control
0xA0
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
PCHCTRL9
Peripheral Clock Control
0xA4
32
read-write
n
0x0
0x0
CHEN
Channel Enable
6
1
GEN
Generic Clock Generator
0
3
GENSelect
GCLK0
Generic clock generator 0
0x0
GCLK1
Generic clock generator 1
0x1
GCLK2
Generic clock generator 2
0x2
GCLK3
Generic clock generator 3
0x3
GCLK4
Generic clock generator 4
0x4
WRTLOCK
Write Lock
7
1
SYNCBUSY
Synchronization Busy
0x4
32
read-only
n
0x0
0x0
GENCTRL0
Generic Clock Generator Control 0 Synchronization Busy bit
2
1
GENCTRL1
Generic Clock Generator Control 1 Synchronization Busy bit
3
1
GENCTRL2
Generic Clock Generator Control 2 Synchronization Busy bit
4
1
GENCTRL3
Generic Clock Generator Control 3 Synchronization Busy bit
5
1
GENCTRL4
Generic Clock Generator Control 4 Synchronization Busy bit
6
1
SWRST
Software Reset Synchroniation Busy bit
0
1
ICB
Implementation Control Block
ICB
0x0
0x0
0xC
registers
n
ACTLR
Auxiliary Control Register
0x8
32
read-write
n
0x0
0x0
ICTR
Interrupt Controller Type Register
0x4
32
read-only
n
0x0
0x0
INTLINESNUM
Interrupt line set number
0
4
IDAU
Implementation Defined Attribution Unit
IDAU
0x0
0x0
0x1
reserved
n
MCLK
Main Clock
MCLK
0x0
0x0
0x20
registers
n
AHBMASK
AHB Mask
0x10
32
read-write
n
0x0
0x0
APBA_
AHB-APB Bridge A AHB Clock Mask
0
1
APBB_
AHB-APB Bridge B AHB Clock Mask
1
1
APBC_
AHB-APB Bridge C AHB Clock Mask
2
1
DMAC_
DMAC AHB Clock Mask
3
1
DSU_
DSU AHB Clock Mask
4
1
HPB0_
HPB0 AHB Clock Mask
0
1
HPB1_
HPB1 AHB Clock Mask
1
1
HPB2_
HPB2 AHB Clock Mask
2
1
NVMCTRL_
NVMCTRL AHB Clock Mask
7
1
PAC_
PAC AHB Clock Mask
6
1
TRAM_
TRAM AHB Clock Mask
12
1
APBAMASK
APBA Mask
0x14
32
read-write
n
0x0
0x0
AC_
AC APB Clock Enable
13
1
EIC_
EIC APB Clock Enable
10
1
FREQM_
FREQM APB Clock Enable
11
1
GCLK_
GCLK APB Clock Enable
7
1
MCLK_
MCLK APB Clock Enable
2
1
OSC32KCTRL_
OSC32KCTRL APB Clock Enable
5
1
OSCCTRL_
OSCCTRL APB Clock Enable
4
1
PAC_
PAC APB Clock Enable
0
1
PM_
PM APB Clock Enable
1
1
PORT_
PORT APB Clock Enable
12
1
RSTC_
RSTC APB Clock Enable
3
1
RTC_
RTC APB Clock Enable
9
1
SUPC_
SUPC APB Clock Enable
6
1
WDT_
WDT APB Clock Enable
8
1
APBBMASK
APBB Mask
0x18
32
read-write
n
0x0
0x0
DSU_
DSU APB Clock Enable
1
1
HMATRIXS_
HMATRIXHS APBB Clock Enable
4
1
IDAU_
IDAU APB Clock Enable
0
1
NVMCTRL_
NVMCTRL APB Clock Enable
2
1
APBCMASK
APBC Mask
0x1C
32
read-write
n
0x0
0x0
ADC_
ADC APB Clock Enable
7
1
CCL_
CCL APB Clock Enable
11
1
DAC_
DAC APB Clock Enable
8
1
EVSYS_
EVSYS APB Clock Enable
0
1
OPAMP_
OPAMP APB Clock Enable
12
1
PTC_
PTC APB Clock Enable
9
1
SERCOM0_
SERCOM0 APB Clock Enable
1
1
SERCOM1_
SERCOM1 APB Clock Enable
2
1
SERCOM2_
SERCOM2 APB Clock Enable
3
1
TC0_
TC0 APB Clock Enable
4
1
TC1_
TC1 APB Clock Enable
5
1
TC2_
TC2 APB Clock Enable
6
1
TRNG_
TRNG APB Clock Enable
10
1
CPUDIV
CPU Clock Division
0x4
8
read-write
n
0x0
0x0
CPUDIV
CPU Clock Division Factor
0
8
CPUDIVSelect
DIV1
Divide by 1
0x01
DIV2
Divide by 2
0x02
DIV4
Divide by 4
0x04
DIV8
Divide by 8
0x08
DIV16
Divide by 16
0x10
DIV32
Divide by 32
0x20
DIV64
Divide by 64
0x40
DIV128
Divide by 128
0x80
CTRLA
Control
0x0
8
read-write
n
0x0
0x0
CKSEL
Clock Select
2
1
INTENCLR
Interrupt Enable Clear
0x1
8
read-write
n
0x0
0x0
CKRDY
Clock Ready Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x2
8
read-write
n
0x0
0x0
CKRDY
Clock Ready Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x3
8
read-write
n
0x0
0x0
CKRDY
Clock Ready
0
1
MPU
Memory Protection Unit
MPU
0x0
0x0
0x38
registers
n
CTRL
MPU Control Register
0x4
32
read-write
n
0x0
0x0
ENABLE
MPU enable
0
1
HFNMIENA
HardFault, NMI enable
1
1
PRIVDEFENA
Privileged default enable
2
1
MAIR0
MPU Memory Attribute Indirection Register 0
0x30
32
read-write
n
0x0
0x0
Attr0
Attribute of MPU region 0
0
8
Attr1
Attribute of MPU region 1
8
8
Attr2
Attribute of MPU region 2
16
8
Attr3
Attribute of MPU region 3
24
8
MAIR1
MPU Memory Attribute Indirection Register 1
0x34
32
read-write
n
0x0
0x0
Attr4
Memory attribute encoding for MPU regions with AttrIndx 4
0
8
Attr5
Memory attribute encoding for MPU regions with AttrIndx 5
8
8
Attr6
Memory attribute encoding for MPU regions with AttrIndx 6
16
8
Attr7
Memory attribute encoding for MPU regions with AttrIndx 7
24
8
RBAR
MPU Region Base Address Register
0xC
32
read-write
n
0x0
0x0
AP
Access permissions
1
2
APSelect
RWPRIV
Read/write by privileged code only
0
0x0
Read/write by privileged code only
0x0
0x1
Read/write by any privilege level
0x1
0x2
Read-only by privileged code only
0x2
0x3
Read-only by any privilege level
0x3
RWANY
Read/write by any privilege level
1
RPRIV
Read-only by privileged code only
2
RANY
Read-only by any privilege level
3
BASE
Base address
5
27
SH
Shareability
3
2
SHSelect
NO
Non-shareable
0
NON
Non-shareable
0x0
OUTER
Outer shareable
2
INNER
Inner shareable
3
XN
Execute Never
0
1
XNSelect
0x0
Execution only permitted if read permitted
0x0
0x1
Execution not permitted
0x1
RLAR
MPU Region Limit Address Register
0x10
32
read-write
n
0x0
0x0
AttrInd
Attribute Index
1
3
EN
Region enable
0
1
LIMIT
Limit address
5
27
RNR
MPU Region Number Register
0x8
32
read-write
n
0x0
0x0
REGION
Selected region number
0
8
TYPE
MPU Type Register
0x0
32
read-only
n
0x0
0x0
DREGION
Number of MPU data regions
8
8
SEPARATE
Separate instructions and data address regions
0
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x348
registers
n
IABR0
Interrupt Active Bit Register n
0x200
32
read-only
n
0x0
0x0
ACTIVE
Active state
0
32
IABR1
Interrupt Active Bit Register n
0x204
32
read-only
n
0x0
0x0
ACTIVE
Active state
0
32
ICER0
Interrupt Clear Enable Register n
0x80
32
read-write
n
0x0
0x0
CLRENA
Clear enable
0
32
ICER1
Interrupt Clear Enable Register n
0x84
32
read-write
n
0x0
0x0
CLRENA
Clear enable
0
32
ICPR0
Interrupt Clear Pending Register n
0x180
32
read-write
n
0x0
0x0
CLRPEND
Clear pending
0
32
ICPR1
Interrupt Clear Pending Register n
0x184
32
read-write
n
0x0
0x0
CLRPEND
Clear pending
0
32
IPR0
Interrupt Priority Register n
0x300
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR1
Interrupt Priority Register n
0x304
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR10
Interrupt Priority Register n
0x328
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR11
Interrupt Priority Register n
0x32C
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR2
Interrupt Priority Register n
0x308
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR3
Interrupt Priority Register n
0x30C
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR4
Interrupt Priority Register n
0x310
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR5
Interrupt Priority Register n
0x314
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR6
Interrupt Priority Register n
0x318
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR7
Interrupt Priority Register n
0x31C
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR8
Interrupt Priority Register n
0x320
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
IPR9
Interrupt Priority Register n
0x324
32
read-write
n
0x0
0x0
PRI0
Priority of interrupt n
0
2
PRI1
Priority of interrupt n
8
2
PRI2
Priority of interrupt n
16
2
PRI3
Priority of interrupt n
24
2
PRI_N0
Priority of interrupt number 4n+0
0
8
PRI_N1
Priority of interrupt number 4n+1
8
8
PRI_N2
Priority of interrupt number 4n+2
16
8
PRI_N3
Priority of interrupt number 4n+3
24
8
ISER0
Interrupt Set Enable Register n
0x0
32
read-write
n
0x0
0x0
SETENA
Set enable
0
32
ISER1
Interrupt Set Enable Register n
0x4
32
read-write
n
0x0
0x0
SETENA
Set enable
0
32
ISPR0
Interrupt Set Pending Register n
0x100
32
read-write
n
0x0
0x0
SETPEND
Set pending
0
32
ISPR1
Interrupt Set Pending Register n
0x104
32
read-write
n
0x0
0x0
SETPEND
Set pending
0
32
ITNS0
Interrupt Target Non-secure Register n
0x280
32
read-write
n
0x0
0x0
ITNS
Interrupt Targets Non-secure
0
32
ITNS1
Interrupt Target Non-secure Register n
0x284
32
read-write
n
0x0
0x0
ITNS
Interrupt Targets Non-secure
0
32
NVMCTRL
Non-Volatile Memory Controller
NVMCTRL
0x0
0x0
0x48
registers
n
NVMCTRL
9
ADDR
Address
0x1C
32
read-write
n
0x0
0x0
AOFFSET
NVM Address Offset In The Selected Array
0
16
ARRAY
Array Select
22
2
ARRAYSelect
FLASH
FLASH Array
0x0
DATAFLASH
DATA FLASH Array
0x1
AUX
Auxilliary Space
0x2
NVMROWS
NVM Rows
0x2
CTRLA
Control A
0x0
16
write-only
n
0x0
0x0
CMD
Command
0
7
CMDSelect
ER
Erase Row - Erases the row addressed by the ADDR register.
0x02
WP
Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
0x04
SPRM
Sets the power reduction mode.
0x42
CPRM
Clears the power reduction mode.
0x43
PBC
Page Buffer Clear - Clears the page buffer.
0x44
INVALL
Invalidate all cache lines.
0x46
SDAL0
Set DAL=0
0x4B
SDAL1
Set DAL=1
0x4C
CMDEX
Command Execution
8
8
CMDEXSelect
KEY
Execution Key
0xA5
CTRLB
Control B
0x4
32
read-write
n
0x0
0x0
CACHEDIS
Cache Disable
18
1
FWUP
fast wake-up
11
1
QWEN
Quick Write Enable
19
1
READMODE
NVMCTRL Read Mode
16
2
READMODESelect
NO_MISS_PENALTY
The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
0x0
LOW_POWER
Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
0x1
DETERMINISTIC
The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
0x2
RWS
NVM Read Wait States
1
4
SLEEPPRM
Power Reduction Mode during Sleep
8
2
SLEEPPRMSelect
WAKEONACCESS
NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.
0
WAKEUPINSTANT
NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.
1
DISABLED
Auto power reduction disabled.
3
CTRLC
Control C
0x8
8
read-write
n
0x0
0x0
MANW
Manual Write
0
1
DSCC
Data Scramble Configuration
0x30
32
write-only
n
0x0
0x0
DSCKEY
Data Scramble Key
0
30
EVCTRL
Event Control
0xA
8
read-write
n
0x0
0x0
AUTOWEI
Auto Write Event Enable
0
1
AUTOWINV
Auto Write Event Polarity Inverted
1
1
INTENCLR
Interrupt Enable Clear
0xC
8
read-write
n
0x0
0x0
DONE
NVM Done Interrupt Clear
0
1
KEYE
Key Write Error Interrupt Clear
4
1
LOCKE
Lock Error Status Interrupt Clear
2
1
NSCHK
NS configuration change detected Interrupt Clear
5
1
NVME
NVM Error Interrupt Clear
3
1
PROGE
Programming Error Status Interrupt Clear
1
1
INTENSET
Interrupt Enable Set
0x10
8
read-write
n
0x0
0x0
DONE
NVM Done Interrupt Enable
0
1
KEYE
Key Write Error Interrupt Enable
4
1
LOCKE
Lock Error Status Interrupt Enable
2
1
NSCHK
NS configuration change detected Interrupt Enable
5
1
NVME
NVM Error Interrupt Enable
3
1
PROGE
Programming Error Status Interrupt Enable
1
1
INTFLAG
Interrupt Flag Status and Clear
0x14
8
read-write
n
0x0
0x0
DONE
NVM Done
0
1
KEYE
KEY Write Error
4
1
LOCKE
Lock Error Status
2
1
NSCHK
NS configuration change detected
5
1
NVME
NVM Error
3
1
PROGE
Programming Error Status
1
1
NONSEC
Non-secure Write Enable
0x40
32
read-write
n
0x0
0x0
WRITE
Non-secure APB alias write enable, non-secure AHB writes to non-secure regions enable
0
1
NSCHK
Non-secure Write Reference Value
0x44
32
read-write
n
0x0
0x0
WRITE
Reference value to be checked against NONSEC.WRITE
0
1
NSULCK
Non-Secure Unlock Register
0x22
16
read-write
n
0x0
0x0
ANS
Non-Secure Application Region
1
1
BNS
Non-Secure Boot Region
0
1
DNS
Non-Secure Data Region
2
1
NSLKEY
Write Key
8
8
NSLKEYSelect
KEY
Write Key
0xA5
PARAM
NVM Parameter
0x24
32
read-write
n
0x0
0x0
DFLASHP
DATAFLASH Pages
20
12
FLASHP
FLASH Pages
0
16
PSZ
Page Size
16
3
PSZSelect
8
8 bytes
0x0
16
16 bytes
0x1
32
32 bytes
0x2
64
64 bytes
0x3
128
128 bytes
0x4
256
256 bytes
0x5
512
512 bytes
0x6
1024
1024 bytes
0x7
SCFGAD
Secure Application and Data Configuration
0x3C
32
read-write
n
0x0
0x0
URWEN
User Row Write Enable
0
1
SCFGB
Secure Boot Configuration
0x38
32
read-write
n
0x0
0x0
BCREN
Boot Configuration Row Read Enable
0
1
BCWEN
Boot Configuration Row Write Enable
1
1
SECCTRL
Security Control
0x34
32
read-write
n
0x0
0x0
DSCEN
Data Scramble Enable
3
1
DXN
Data Flash is eXecute Never
6
1
KEY
Write Key
24
8
KEYSelect
KEY
Write Key
0xA5
SILACC
Silent Access
2
1
TAMPEEN
Tamper Erase Enable
0
1
TEROW
Tamper Rease Row
8
3
STATUS
Status
0x18
16
read-only
n
0x0
0x0
DALFUSE
Debug Access Level Fuse
3
2
DALFUSESelect
DAL0
NO DEBUG
0x0
DAL2
FULL DEBUG
0x2
LOAD
NVM Page Buffer Active Loading
1
1
PRM
Power Reduction Mode
0
1
READY
NVM Ready
2
1
SULCK
Secure Unlock Register
0x20
16
read-write
n
0x0
0x0
AS
Secure Application Region
1
1
BS
Secure Boot Region
0
1
DS
Data Secure Region
2
1
SLKEY
Write Key
8
8
SLKEYSelect
KEY
Write Key
0xA5
OPAMP
Operational Amplifier
OPAMP
0x0
0x0
0x11
registers
n
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
LPMUX
Low-Power Mux
7
1
SWRST
Software Reset
0
1
OPAMPCTRL0
OPAMP0 Control
0x4
32
read-write
n
0x0
0x0
ANAOUT
Analog Output
2
1
BIAS
Bias Selection
3
2
ENABLE
Operational Amplifier Enable
1
1
MUXNEG
Negative Input Mux Selection
20
4
MUXNEGSelect
OA0NEG
Negative I/O pin
0
OA0TAP
Resistor ladder 0 taps
1
REFERENCE_DAC
REFERENCE or DAC output
2
OA0OUT
OPAMP0 output
3
MUXPOS
Positive Input Mux Selection
16
4
MUXPOSSelect
OA0POS
Positive I/O pin
0
OA0TAP
Resistor ladder 0 taps
1
REFERENCE_DAC
REFERENCE or DAC output
2
GND
Ground
3
ONDEMAND
On Demand Control
7
1
POTMUX
Potentiometer Selection
13
3
POTMUXSelect
14R_2R
R1 = 14R, R2 = 2R
0
12R_4R
R1 = 12R, R2 = 4R
1
8R_8R
R1 = 8R, R2 = 8R
2
6R_10R
R1 = 6R, R2 = 10R
3
4R_12R
R1 = 4R, R2 = 12R
4
3R_13R
R1 = 3R, R2 = 13R
5
2R_14R
R1 = 2R, R2 = 14R
6
R_15R
R1 = 1R, R2 = 15R
7
RES1EN
Resistor 1 Enable
9
1
RES1MUX
Resistor 1 Mux
10
3
RES1MUXSelect
OAxPOS
Positive inout of OPAMPx
0
OAxNEG
Negative input of OPAMPx
1
DAC
DAC output
2
GND
Ground
3
RG_CONN
RG_CONN
4
RES2OUT
Resistor ladder To Output
8
1
RES2VCC
Resistor ladder To VCC
5
1
RUNSTDBY
Run in Standby
6
1
OPAMPCTRL1
OPAMP1 Control
0x8
32
read-write
n
0x0
0x0
ANAOUT
Analog Output
2
1
BIAS
Bias Selection
3
2
ENABLE
Operational Amplifier Enable
1
1
MUXNEG
Negative Input Mux Selection
20
4
MUXNEGSelect
OA0NEG
Negative I/O pin
0
OA0TAP
Resistor ladder 0 taps
1
REFERENCE_DAC
REFERENCE or DAC output
2
OA0OUT
OPAMP0 output
3
MUXPOS
Positive Input Mux Selection
16
4
MUXPOSSelect
OA1POS
Positive I/O pin
0
OA1TAP
Resistor ladder 1 taps
1
REFERENCE_DAC
REFERENCE or DAC output
2
GND
Ground
3
OA0OUT
OPAMP0 output
4
ONDEMAND
On Demand Control
7
1
POTMUX
Potentiometer Selection
13
3
POTMUXSelect
14R_2R
R1 = 14R, R2 = 2R
0
12R_4R
R1 = 12R, R2 = 4R
1
8R_8R
R1 = 8R, R2 = 8R
2
6R_10R
R1 = 6R, R2 = 10R
3
4R_12R
R1 = 4R, R2 = 12R
4
3R_13R
R1 = 3R, R2 = 13R
5
2R_14R
R1 = 2R, R2 = 14R
6
R_15R
R1 = 1R, R2 = 15R
7
RES1EN
Resistor 1 Enable
9
1
RES1MUX
Resistor 1 Mux
10
3
RES1MUXSelect
OAxPOS
Positive inout of OPAMPx
0
OAxNEG
Negative input of OPAMPx
1
OA0OUT
OPAMP0 output
2
GND
Ground
3
RG_CONN
RG_CONN
4
RES2OUT
Resistor ladder To Output
8
1
RES2VCC
Resistor ladder To VCC
5
1
RUNSTDBY
Run in Standby
6
1
OPAMPCTRL2
OPAMP2 Control
0xC
32
read-write
n
0x0
0x0
ANAOUT
Analog Output
2
1
BIAS
Bias Selection
3
2
ENABLE
Operational Amplifier Enable
1
1
MUXNEG
Negative Input Mux Selection
20
4
MUXNEGSelect
OA0NEG
Negative I/O pin
0
OA0TAP
Resistor ladder 0 taps
1
REFERENCE_DAC
REFERENCE or DAC output
2
OA0OUT
OPAMP0 output
3
MUXPOS
Positive Input Mux Selection
16
4
MUXPOSSelect
OA2POS
Positive I/O pin
0
OA2TAP
Resistor ladder 2 taps
1
REFERENCE_DAC
REFERENCE or DAC output
2
GND
Ground
3
OA1OUT
OPAMP1 output
4
OA0POS
Positive I/O pin OPA0
5
OA1POS
Positive I/O pin OPA1
6
OA0TAP
OPAMP0 Resistor Ladder Taps
7
RES3TAP
Resistor ladder 3 taps
7
ONDEMAND
On Demand Control
7
1
POTMUX
Potentiometer Selection
13
3
POTMUXSelect
14R_2R
R1 = 14R, R2 = 2R
0
12R_4R
R1 = 12R, R2 = 4R
1
8R_8R
R1 = 8R, R2 = 8R
2
6R_10R
R1 = 6R, R2 = 10R
3
4R_12R
R1 = 4R, R2 = 12R
4
3R_13R
R1 = 3R, R2 = 13R
5
2R_14R
R1 = 2R, R2 = 14R
6
R_15R
R1 = 1R, R2 = 15R
7
RES1EN
Resistor 1 Enable
9
1
RES1MUX
Resistor 1 Mux
10
3
RES1MUXSelect
OAxPOS
Positive inout of OPAMPx
0
OAxNEG
Negative input of OPAMPx
1
OA1OUT
OPAMP1 output
2
GND
Ground
3
RES2OUT
Resistor ladder To Output
8
1
RES2VCC
Resistor ladder To VCC
5
1
RUNSTDBY
Run in Standby
6
1
RESCTRL
Resister Control
0x10
8
read-write
n
0x0
0x0
POTMUX
Potentiometer Selection
3
3
POTMUXSelect
14R_2R
Gain = 0.14
0
12R_4R
Gain = 0.33
1
8R_8R
Gain = 1
2
6R_10R
Gain = 1.67
3
4R_12R
Gain = 3
4
3R_13R
Gain = 4.33
5
2R_14R
Gain = 7
6
R_15R
Gain = 15
7
REFBUFLEVEL
Reference output voltage level select
6
2
REFBUFLEVELSelect
1_1v
1.1v
0
1_25v
1.25v
1
1_6v
1.6v
2
RES1EN
Resistor 1 Enable
1
1
RES1MUX
Resistor 1 Mux
2
1
RES1MUXSelect
DAC
DAC output
0
REFBUF
REFERENCE output
1
RES2OUT
Resistor ladder To Output
0
1
STATUS
Status
0x2
8
read-only
n
0x0
0x0
READY0
OPAMP 0 Ready
0
1
READY1
OPAMP 1 Ready
1
1
READY2
OPAMP 2 Ready
2
1
OSC32KCTRL
32k Oscillators Control
OSC32KCTRL
0x0
0x0
0x20
registers
n
CFDCTRL
Clock Failure Detector Control
0x16
8
read-write
n
0x0
0x0
CFDEN
Clock Failure Detector Enable
0
1
CFDPRESC
Clock Failure Detector Prescaler
2
1
SWBACK
Clock Switch Back
1
1
EVCTRL
Event Control
0x17
8
read-write
n
0x0
0x0
CFDEO
Clock Failure Detector Event Output Enable
0
1
CLKFAILEO
Clock Failure Detector Event Output Enable
0
1
INTENCLR
Interrupt Enable Clear
0x0
32
read-write
n
0x0
0x0
CLKFAIL
XOSC32K Clock Failure Detector Interrupt Enable
2
1
XOSC32KRDY
XOSC32K Ready Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x4
32
read-write
n
0x0
0x0
CLKFAIL
XOSC32K Clock Failure Detector Interrupt Enable
2
1
XOSC32KRDY
XOSC32K Ready Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x8
32
read-write
n
0x0
0x0
CLKFAIL
XOSC32K Clock Failure Detector
2
1
XOSC32KRDY
XOSC32K Ready
0
1
OSCULP32K
32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
0x1C
32
read-write
n
0x0
0x0
CALIB
Oscillator Calibration
8
5
ULP32KSW
OSCULP32K Clock Switch Enable
5
1
WRTLOCK
Write Lock
15
1
RTCCTRL
RTC Clock Selection
0x10
8
read-write
n
0x0
0x0
RTCSEL
RTC Clock Selection
0
3
RTCSELSelect
ULP1K
1.024kHz from 32kHz internal ULP oscillator
0
ULP32K
32.768kHz from 32kHz internal ULP oscillator
1
OSC1K
1.024kHz from 32.768kHz internal oscillator
2
OSC32K
32.768kHz from 32.768kHz internal oscillator
3
XOSC1K
1.024kHz from 32.768kHz external oscillator
4
XOSC32K
32.768kHz from 32.768kHz external crystal oscillator
5
STATUS
Power and Clocks Status
0xC
32
read-only
n
0x0
0x0
CLKFAIL
XOSC32K Clock Failure Detector
2
1
CLKSW
XOSC32K Clock switch
3
1
ULP32KSW
OSCULP32K Clock Switch
4
1
XOSC32KRDY
XOSC32K Ready
0
1
XOSC32K
32kHz External Crystal Oscillator (XOSC32K) Control
0x14
16
read-write
n
0x0
0x0
EN1K
1kHz Output Enable
4
1
EN32K
32kHz Output Enable
3
1
ENABLE
Oscillator Enable
1
1
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run in Standby
6
1
STARTUP
Oscillator Start-Up Time
8
3
STARTUPSelect
CYCLE2048
62.5 ms
0
CYCLE4096
125 ms
1
CYCLE16384
500 ms
2
CYCLE32768
1000 ms
3
CYCLE65536
2000 ms
4
CYCLE131072
4000 ms
5
CYCLE262144
8000 ms
6
WRTLOCK
Write Lock
12
1
XTALEN
Crystal Oscillator Enable
2
1
OSCCTRL
Oscillators Control
OSCCTRL
0x0
0x0
0x41
registers
n
CFDPRESC
Clock Failure Detector Prescaler
0x16
8
read-write
n
0x0
0x0
CFDPRESC
Clock Failure Detector Prescaler
0
3
CFDPRESCSelect
DIV1
OSC16M/1
0
DIV2
OSC16M/2
1
DIV4
OSC16M/4
2
DIV8
OSC16M/8
3
DIV16
OSC16M/16
4
DIV32
OSC16M/32
5
DIV64
OSC16M/64
6
DIV128
OSC16M/128
7
DFLLULPCTRL
DFLLULP Control
0x1C
16
read-write
n
0x0
0x0
BINSE
Binary Search Enable
3
1
DITHER
Tuner Dither Mode
5
1
DIV
Division Factor
8
3
DIVSelect
DIV1
Frequency Divided by 1
0x0
DIV2
Frequency Divided by 2
0x1
DIV4
Frequency Divided by 4
0x2
DIV8
Frequency Divided by 8
0x3
DIV16
Frequency Divided by 16
0x4
DIV32
Frequency Divided by 32
0x5
ENABLE
Enable
1
1
ONDEMAND
On Demand
7
1
RUNSTDBY
Run in Standby
6
1
SAFE
Tuner Safe Mode
4
1
DFLLULPDITHER
DFLLULP Dither Control
0x1E
8
read-write
n
0x0
0x0
PER
Dither Period
4
3
PERSelect
PER1
Dither Over 1 Reference Clock Period
0x0
PER2
Dither Over 2 Reference Clock Period
0x1
PER4
Dither Over 4 Reference Clock Period
0x2
PER8
Dither Over 8 Reference Clock Period
0x3
PER16
Dither Over 16 Reference Clock Period
0x4
PER32
Dither Over 32 Reference Clock Period
0x5
STEP
Dither Step
0
3
STEPSelect
STEP1
Dither Step = 1
0x0
STEP2
Dither Step = 2
0x1
STEP4
Dither Step = 4
0x2
STEP8
Dither Step = 8
0x3
DFLLULPDLY
DFLLULP Delay Value
0x20
32
read-write
n
0x0
0x0
DELAY
Delay Value
0
8
DFLLULPRATIO
DFLLULP Target Ratio
0x24
32
read-write
n
0x0
0x0
RATIO
Target Tuner Ratio
0
11
DFLLULPRREQ
DFLLULP Read Request
0x1F
8
read-write
n
0x0
0x0
RREQ
Read Request
7
1
DFLLULPSYNCBUSY
DFLLULP Synchronization Busy
0x28
32
read-only
n
0x0
0x0
DELAY
Delay Register Synchronization Busy
3
1
ENABLE
Enable Bit Synchronization Busy
1
1
TUNE
Tune Bit Synchronization Busy
2
1
DPLLCTRLA
DPLL Control A
0x2C
8
read-write
n
0x0
0x0
ENABLE
DPLL Enable
1
1
ONDEMAND
On Demand Clock Activation
7
1
RUNSTDBY
Run in Standby
6
1
DPLLCTRLB
DPLL Control B
0x34
32
read-write
n
0x0
0x0
DIV
Clock Divider
16
11
FILTER
Proportional Integral Filter Selection
0
2
FILTERSelect
Default
Default Filter Mode
0
LBFILT
Low Bandwidth Filter
1
HBFILT
High Bandwidth Filter
2
HDFILT
High Damping Filter
3
LBYPASS
Lock Bypass
12
1
LPEN
Low-Power Enable
2
1
LTIME
Lock Time
8
3
LTIMESelect
Default
No time-out. Automatic lock
0
8MS
Time-out if no lock within 8 ms
4
9MS
Time-out if no lock within 9 ms
5
10MS
Time-out if no lock within 10 ms
6
11MS
Time-out if no lock within 11 ms
7
REFCLK
Reference Clock Selection
4
2
REFCLKSelect
XOSC32K
XOSC32K Clock Reference
0
XOSC
XOSC Clock Reference
1
GCLK
GCLK Clock Reference
2
WUF
Wake Up Fast
3
1
DPLLPRESC
DPLL Prescaler
0x38
8
read-write
n
0x0
0x0
PRESC
Output Clock Prescaler
0
2
PRESCSelect
DIV1
DPLL output is divided by 1
0
DIV2
DPLL output is divided by 2
1
DIV4
DPLL output is divided by 4
2
DPLLRATIO
DPLL Ratio Control
0x30
32
read-write
n
0x0
0x0
LDR
Loop Divider Ratio
0
12
LDRFRAC
Loop Divider Ratio Fractional Part
16
4
DPLLSTATUS
DPLL Status
0x40
8
read-only
n
0x0
0x0
CLKRDY
DPLL Clock Ready
1
1
LOCK
DPLL Lock
0
1
DPLLSYNCBUSY
DPLL Synchronization Busy
0x3C
8
read-only
n
0x0
0x0
DPLLPRESC
DPLL Prescaler Synchronization Status
3
1
DPLLRATIO
DPLL Loop Divider Ratio Synchronization Status
2
1
ENABLE
DPLL Enable Synchronization Status
1
1
EVCTRL
Event Control
0x0
8
read-write
n
0x0
0x0
CFDEO
Clock Failure Detector Event Output Enable
0
1
TUNEEI
Tune Event Input Enable
1
1
TUNEINV
Tune Event Input Invert
2
1
INTENCLR
Interrupt Enable Clear
0x4
32
read-write
n
0x0
0x0
DFLLULPLOCK
DFLLULP Lock Interrupt Enable
9
1
DFLLULPNOLOCK
DFLLULP No Lock Interrupt Enable
10
1
DFLLULPRDY
DFLLULP Ready interrupt Enable
8
1
DPLLLCKF
DPLL Lock Fall Interrupt Enable
17
1
DPLLLCKR
DPLL Lock Rise Interrupt Enable
16
1
DPLLLDRTO
DPLL Loop Divider Ratio Update Complete Interrupt Enable
19
1
DPLLLTO
DPLL Lock Timeout Interrupt Enable
18
1
OSC16MRDY
OSC16M Ready Interrupt Enable
4
1
XOSCFAIL
XOSC Clock Failure Detector Interrupt Enable
1
1
XOSCRDY
XOSC Ready Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x8
32
read-write
n
0x0
0x0
DFLLULPLOCK
DFLLULP Lock Interrupt Enable
9
1
DFLLULPNOLOCK
DFLLULP No Lock Interrupt Enable
10
1
DFLLULPRDY
DFLLULP Ready interrupt Enable
8
1
DPLLLCKF
DPLL Lock Fall Interrupt Enable
17
1
DPLLLCKR
DPLL Lock Rise Interrupt Enable
16
1
DPLLLDRTO
DPLL Loop Divider Ratio Update Complete Interrupt Enable
19
1
DPLLLTO
DPLL Lock Timeout Interrupt Enable
18
1
OSC16MRDY
OSC16M Ready Interrupt Enable
4
1
XOSCFAIL
XOSC Clock Failure Detector Interrupt Enable
1
1
XOSCRDY
XOSC Ready Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0xC
32
read-write
n
0x0
0x0
DFLLULPLOCK
DFLLULP Lock
9
1
DFLLULPNOLOCK
DFLLULP No Lock
10
1
DFLLULPRDY
DFLLULP Ready
8
1
DPLLLCKF
DPLL Lock Fall
17
1
DPLLLCKR
DPLL Lock Rise
16
1
DPLLLDRTO
DPLL Loop Divider Ratio Update Complete
19
1
DPLLLTO
DPLL Lock Timeout
18
1
OSC16MRDY
OSC16M Ready
4
1
XOSCFAIL
XOSC Clock Failure Detector
1
1
XOSCRDY
XOSC Ready
0
1
OSC16MCTRL
16MHz Internal Oscillator (OSC16M) Control
0x18
8
read-write
n
0x0
0x0
ENABLE
Oscillator Enable
1
1
FSEL
Oscillator Frequency Selection
2
2
FSELSelect
4
4MHz
0x0
8
8MHz
0x1
12
12MHz
0x2
16
16MHz
0x3
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run in Standby
6
1
STATUS
Status
0x10
32
read-only
n
0x0
0x0
DFLLULPLOCK
DFLLULP Lock
9
1
DFLLULPNOLOCK
DFLLULP No Lock
10
1
DFLLULPRDY
DFLLULP Ready
8
1
DPLLLCKF
DPLL Lock Fall
17
1
DPLLLCKR
DPLL Lock Rise
16
1
DPLLLDRTO
DPLL Loop Divider Ratio Update Complete
19
1
DPLLTO
DPLL Lock Timeout
18
1
OSC16MRDY
OSC16M Ready
4
1
XOSCCKSW
XOSC Clock Switch
2
1
XOSCFAIL
XOSC Clock Failure Detector
1
1
XOSCRDY
XOSC Ready
0
1
XOSCCTRL
External Multipurpose Crystal Oscillator (XOSC) Control
0x14
16
read-write
n
0x0
0x0
AMPGC
Automatic Amplitude Gain Control
11
1
CFDEN
Clock Failure Detector Enable
3
1
ENABLE
Oscillator Enable
1
1
GAIN
Oscillator Gain
8
3
GAINSelect
GAIN2
2 MHz
0
GAIN4
4 MHz
1
GAIN8
8 MHz
2
GAIN16
16 MHz
3
GAIN30
30 MHz
4
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run in Standby
6
1
STARTUP
Start-Up Time
12
4
STARTUPSelect
CYCLE1
31 us
0
CYCLE2
61 us
1
CYCLE1024
31250 us
10
CYCLE2048
62500 us
11
CYCLE4096
125000 us
12
CYCLE8192
250000 us
13
CYCLE16384
500000 us
14
CYCLE32768
1000000 us
15
CYCLE4
122 us
2
CYCLE8
244 us
3
CYCLE16
488 us
4
CYCLE32
977 us
5
CYCLE64
1953 us
6
CYCLE128
3906 us
7
CYCLE256
7813 us
8
CYCLE512
15625 us
9
SWBEN
Xosc Clock Switch Enable
4
1
XTALEN
Crystal Oscillator Enable
2
1
PAC
Peripheral Access Controller
PAC
0x0
0x0
0x60
registers
n
0x0
0x60
registers
n
PAC
21
EVCTRL
Event control
0x4
8
read-write
n
0x0
0x0
ERREO
Peripheral acess error event output
0
1
INTENCLR
Interrupt enable clear
0x8
8
read-write
n
0x0
0x0
ERR
Peripheral access error interrupt disable
0
1
INTENSET
Interrupt enable set
0x9
8
read-write
n
0x0
0x0
ERR
Peripheral access error interrupt enable
0
1
INTFLAGA
Peripheral interrupt flag status - Bridge A
0x14
32
read-write
n
0x0
0x0
AC_
AC
13
1
EIC_
EIC
10
1
FREQM_
FREQM
11
1
GCLK_
GCLK
7
1
MCLK_
MCLK
2
1
OSC32KCTRL_
OSC32KCTRL
5
1
OSCCTRL_
OSCCTRL
4
1
PAC_
PAC
0
1
PM_
PM
1
1
PORT_
PORT
12
1
RSTC_
RSTC
3
1
RTC_
RTC
9
1
SUPC_
SUPC
6
1
WDT_
WDT
8
1
INTFLAGAHB
Bridge interrupt flag status
0x10
32
read-write
n
0x0
0x0
APBA_
AHB-APB Bridge A
1
1
APBB_
AHB-APB Bridge B
2
1
APBC_
AHB-APB Bridge C
3
1
BROM_
BROM
7
1
FLASH_
FLASH
0
1
HPB0_
HPB0
1
1
HPB1_
HPB1
2
1
HPB2_
HPB2
3
1
HSRAMCPU_
HSRAMCPU
4
1
HSRAMDMAC_
HSRAMDMAC
5
1
HSRAMDSU_
HSRAMDSU
6
1
INTFLAGB
Peripheral interrupt flag status - Bridge B
0x18
32
read-write
n
0x0
0x0
DMAC_
DMAC
3
1
DSU_
DSU
1
1
IDAU_
IDAU
0
1
NVMCTRL_
NVMCTRL
2
1
INTFLAGC
Peripheral interrupt flag status - Bridge C
0x1C
32
read-write
n
0x0
0x0
ADC_
ADC
7
1
CCL_
CCL
11
1
DAC_
DAC
8
1
EVSYS_
EVSYS
0
1
OPAMP_
OPAMP
12
1
PTC_
PTC
9
1
SERCOM0_
SERCOM0
1
1
SERCOM1_
SERCOM1
2
1
SERCOM2_
SERCOM2
3
1
TC0_
TC0
4
1
TC1_
TC1
5
1
TC2_
TC2
6
1
TRAM_
TRAM
13
1
TRNG_
TRNG
10
1
NONSECA
Peripheral non-secure status - Bridge A
0x54
32
read-only
n
0x0
0x0
AC_
AC Non-Secure
13
1
EIC_
EIC Non-Secure
10
1
FREQM_
FREQM Non-Secure
11
1
GCLK_
GCLK Non-Secure
7
1
MCLK_
MCLK Non-Secure
2
1
OSC32KCTRL_
OSC32KCTRL Non-Secure
5
1
OSCCTRL_
OSCCTRL Non-Secure
4
1
PAC_
PAC Non-Secure
0
1
PM_
PM Non-Secure
1
1
PORT_
PORT Non-Secure
12
1
RSTC_
RSTC Non-Secure
3
1
RTC_
RTC Non-Secure
9
1
SUPC_
SUPC Non-Secure
6
1
WDT_
WDT Non-Secure
8
1
NONSECB
Peripheral non-secure status - Bridge B
0x58
32
read-only
n
0x0
0x0
DMAC_
DMAC Non-Secure
3
1
DSU_
DSU Non-Secure
1
1
IDAU_
IDAU Non-Secure
0
1
NVMCTRL_
NVMCTRL Non-Secure
2
1
NONSECC
Peripheral non-secure status - Bridge C
0x5C
32
read-only
n
0x0
0x0
ADC_
ADC Non-Secure
7
1
CCL_
CCL Non-Secure
11
1
DAC_
DAC Non-Secure
8
1
EVSYS_
EVSYS Non-Secure
0
1
OPAMP_
OPAMP Non-Secure
12
1
PTC_
PTC Non-Secure
9
1
SERCOM0_
SERCOM0 Non-Secure
1
1
SERCOM1_
SERCOM1 Non-Secure
2
1
SERCOM2_
SERCOM2 Non-Secure
3
1
TC0_
TC0 Non-Secure
4
1
TC1_
TC1 Non-Secure
5
1
TC2_
TC2 Non-Secure
6
1
TRAM_
TRAM Non-Secure
13
1
TRNG_
TRNG Non-Secure
10
1
SECLOCKA
Peripheral secure status locked - Bridge A
0x74
32
read-only
n
0x0
0x0
AC_
AC Secure Status Locked
13
1
EIC_
EIC Secure Status Locked
10
1
FREQM_
FREQM Secure Status Locked
11
1
GCLK_
GCLK Secure Status Locked
7
1
MCLK_
MCLK Secure Status Locked
2
1
OSC32KCTRL_
OSC32KCTRL Secure Status Locked
5
1
OSCCTRL_
OSCCTRL Secure Status Locked
4
1
PAC_
PAC Secure Status Locked
0
1
PM_
PM Secure Status Locked
1
1
PORT_
PORT Secure Status Locked
12
1
RSTC_
RSTC Secure Status Locked
3
1
RTC_
RTC Secure Status Locked
9
1
SUPC_
SUPC Secure Status Locked
6
1
WDT_
WDT Secure Status Locked
8
1
SECLOCKB
Peripheral secure status locked - Bridge B
0x78
32
read-only
n
0x0
0x0
DMAC_
DMAC Secure Status Locked
3
1
DSU_
DSU Secure Status Locked
1
1
IDAU_
IDAU Secure Status Locked
0
1
NVMCTRL_
NVMCTRL Secure Status Locked
2
1
SECLOCKC
Peripheral secure status locked - Bridge C
0x7C
32
read-only
n
0x0
0x0
ADC_
ADC Secure Status Locked
7
1
CCL_
CCL Secure Status Locked
11
1
DAC_
DAC Secure Status Locked
8
1
EVSYS_
EVSYS Secure Status Locked
0
1
OPAMP_
OPAMP Secure Status Locked
12
1
PTC_
PTC Secure Status Locked
9
1
SERCOM0_
SERCOM0 Secure Status Locked
1
1
SERCOM1_
SERCOM1 Secure Status Locked
2
1
SERCOM2_
SERCOM2 Secure Status Locked
3
1
TC0_
TC0 Secure Status Locked
4
1
TC1_
TC1 Secure Status Locked
5
1
TC2_
TC2 Secure Status Locked
6
1
TRAM_
TRAM Secure Status Locked
13
1
TRNG_
TRNG Secure Status Locked
10
1
STATUSA
Peripheral write protection status - Bridge A
0x34
32
read-only
n
0x0
0x0
AC_
AC APB Protect Enable
13
1
EIC_
EIC APB Protect Enable
10
1
FREQM_
FREQM APB Protect Enable
11
1
GCLK_
GCLK APB Protect Enable
7
1
MCLK_
MCLK APB Protect Enable
2
1
OSC32KCTRL_
OSC32KCTRL APB Protect Enable
5
1
OSCCTRL_
OSCCTRL APB Protect Enable
4
1
PAC_
PAC APB Protect Enable
0
1
PM_
PM APB Protect Enable
1
1
PORT_
PORT APB Protect Enable
12
1
RSTC_
RSTC APB Protect Enable
3
1
RTC_
RTC APB Protect Enable
9
1
SUPC_
SUPC APB Protect Enable
6
1
WDT_
WDT APB Protect Enable
8
1
STATUSB
Peripheral write protection status - Bridge B
0x38
32
read-only
n
0x0
0x0
DMAC_
DMAC APB Protect Enable
3
1
DSU_
DSU APB Protect Enable
1
1
IDAU_
IDAU APB Protect Enable
0
1
NVMCTRL_
NVMCTRL APB Protect Enable
2
1
STATUSC
Peripheral write protection status - Bridge C
0x3C
32
read-only
n
0x0
0x0
ADC_
ADC APB Protect Enable
7
1
CCL_
CCL APB Protect Enable
11
1
DAC_
DAC APB Protect Enable
8
1
EVSYS_
EVSYS APB Protect Enable
0
1
OPAMP_
OPAMP APB Protect Enable
12
1
PTC_
PTC APB Protect Enable
9
1
SERCOM0_
SERCOM0 APB Protect Enable
1
1
SERCOM1_
SERCOM1 APB Protect Enable
2
1
SERCOM2_
SERCOM2 APB Protect Enable
3
1
TC0_
TC0 APB Protect Enable
4
1
TC1_
TC1 APB Protect Enable
5
1
TC2_
TC2 APB Protect Enable
6
1
TRAM_
TRAM APB Protect Enable
13
1
TRNG_
TRNG APB Protect Enable
10
1
WRCTRL
Write control
0x0
32
read-write
n
0x0
0x0
KEY
Peripheral access control key
16
8
KEYSelect
OFF
No action
0
CLR
Clear protection
1
CLEAR
Clear protection
1
SET
Set protection
2
SETLCK
Set and lock protection
3
LOCK
Set and lock protection
3
SETSEC
Set IP secure
4
SETNONSEC
Set IP non-secure
5
SECLOCK
Lock IP security value
6
PERID
Peripheral identifier
0
16
PM
Power Manager
PM
0x0
0x0
0xA
registers
n
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
PLRDY
Performance Level Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
PLRDY
Performance Level Ready interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
PLRDY
Performance Level Ready
0
1
PLCFG
Performance Level Configuration
0x2
8
read-write
n
0x0
0x0
PLDIS
Performance Level Disable
7
1
PLSEL
Performance Level Select
0
2
PLSELSelect
PL0
Performance Level 0
0x0
PL2
Performance Level 2
0x2
PWCFG
Power Configuration
0x3
8
read-write
n
0x0
0x0
RAMPSWC
RAM Power Switch Configuration
0
2
RAMPSWCSelect
16KB
16KB Available
0x0
12KB
12KB Available
0x1
8KB
8KB Available
0x2
4KB
4KB Available
0x3
SLEEPCFG
Sleep Configuration
0x1
8
read-write
n
0x0
0x0
SLEEPMODE
Sleep Mode
0
3
SLEEPMODESelect
IDLE
CPU, AHB, APB clocks are OFF
2
STANDBY
All Clocks are OFF
4
OFF
All power domains are powered OFF
6
STDBYCFG
Standby Configuration
0x8
16
read-write
n
0x0
0x0
BBIASHS
Back Bias for HSRAM
10
1
BBIASTR
Back Bias for Trust RAM
12
1
DPGPDSW
Dynamic Power Gating for PDSW
4
1
DPGPDSWSelect
0
Dynamic Power Gating disabled
0
1
Dynamic Power Gating enabled
1
PDCFG
Power Domain Configuration
0
1
PDCFGSelect
DEFAULT
PDSW power domain switching is handled by hardware.
0
PDSW
PDSW is forced ACTIVE.
1
VREGSMOD
Voltage Regulator Standby mode
6
2
VREGSMODSelect
AUTO
Automatic mode
0
PERFORMANCE
Performance oriented
1
LP
Low Power oriented
2
PORT
Port Module
PORT
0x0
0x0
0x80
registers
n
PORT
10
CTRL
Control
0x24
32
read-write
n
0x0
0x0
SAMPLING
Input Sampling Mode
0
32
DIR
Data Direction
0x0
32
read-write
n
0x0
0x0
DIR
Port Data Direction
0
32
DIRCLR
Data Direction Clear
0x4
32
read-write
n
0x0
0x0
DIRCLR
Port Data Direction Clear
0
32
DIRSET
Data Direction Set
0x8
32
read-write
n
0x0
0x0
DIRSET
Port Data Direction Set
0
32
DIRTGL
Data Direction Toggle
0xC
32
read-write
n
0x0
0x0
DIRTGL
Port Data Direction Toggle
0
32
EVCTRL
Event Input Control
0x2C
32
read-write
n
0x0
0x0
EVACT0
PORT Event Action 0
5
2
EVACT0Select
OUT
Event output to pin
0x0
SET
Set output register of pin on event
0x1
CLR
Clear output register of pin on event
0x2
TGL
Toggle output register of pin on event
0x3
EVACT1
PORT Event Action 1
13
2
EVACT2
PORT Event Action 2
21
2
EVACT3
PORT Event Action 3
29
2
PID0
PORT Event Pin Identifier 0
0
5
PID1
PORT Event Pin Identifier 1
8
5
PID2
PORT Event Pin Identifier 2
16
5
PID3
PORT Event Pin Identifier 3
24
5
PORTEI0
PORT Event Input Enable 0
7
1
PORTEI1
PORT Event Input Enable 1
15
1
PORTEI2
PORT Event Input Enable 2
23
1
PORTEI3
PORT Event Input Enable 3
31
1
IN
Data Input Value
0x20
32
read-only
n
0x0
0x0
IN
PORT Data Input Value
0
32
INTENCLR
Interrupt Enable Clear
0x60
32
read-write
n
0x0
0x0
NSCHK
Non-Secure Check Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x64
32
read-write
n
0x0
0x0
NSCHK
Non-Secure Check Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x68
32
read-write
n
0x0
0x0
NSCHK
Non-Secure Check
0
1
NONSEC
Security Attribution
0x6C
32
read-write
n
0x0
0x0
NONSEC
Port Security Attribution
0
32
NSCHK
Security Attribution Check
0x70
32
read-write
n
0x0
0x0
NSCHK
Port Security Attribution Check
0
32
OUT
Data Output Value
0x10
32
read-write
n
0x0
0x0
OUT
PORT Data Output Value
0
32
OUTCLR
Data Output Value Clear
0x14
32
read-write
n
0x0
0x0
OUTCLR
PORT Data Output Value Clear
0
32
OUTSET
Data Output Value Set
0x18
32
read-write
n
0x0
0x0
OUTSET
PORT Data Output Value Set
0
32
OUTTGL
Data Output Value Toggle
0x1C
32
read-write
n
0x0
0x0
OUTTGL
PORT Data Output Value Toggle
0
32
PINCFG0
Pin Configuration
0x40
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG1
Pin Configuration
0x41
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG10
Pin Configuration
0x4A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG11
Pin Configuration
0x4B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG12
Pin Configuration
0x4C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG13
Pin Configuration
0x4D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG14
Pin Configuration
0x4E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG15
Pin Configuration
0x4F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG16
Pin Configuration
0x50
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG17
Pin Configuration
0x51
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG18
Pin Configuration
0x52
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG19
Pin Configuration
0x53
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG2
Pin Configuration
0x42
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG20
Pin Configuration
0x54
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG21
Pin Configuration
0x55
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG22
Pin Configuration
0x56
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG23
Pin Configuration
0x57
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG24
Pin Configuration
0x58
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG25
Pin Configuration
0x59
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG26
Pin Configuration
0x5A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG27
Pin Configuration
0x5B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG28
Pin Configuration
0x5C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG29
Pin Configuration
0x5D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG3
Pin Configuration
0x43
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG30
Pin Configuration
0x5E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG31
Pin Configuration
0x5F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG4
Pin Configuration
0x44
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG5
Pin Configuration
0x45
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG6
Pin Configuration
0x46
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG7
Pin Configuration
0x47
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG8
Pin Configuration
0x48
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG9
Pin Configuration
0x49
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PMUX0
Peripheral Multiplexing
0x30
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX1
Peripheral Multiplexing
0x31
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX10
Peripheral Multiplexing
0x3A
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX11
Peripheral Multiplexing
0x3B
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX12
Peripheral Multiplexing
0x3C
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX13
Peripheral Multiplexing
0x3D
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX14
Peripheral Multiplexing
0x3E
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX15
Peripheral Multiplexing
0x3F
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX2
Peripheral Multiplexing
0x32
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX3
Peripheral Multiplexing
0x33
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX4
Peripheral Multiplexing
0x34
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX5
Peripheral Multiplexing
0x35
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX6
Peripheral Multiplexing
0x36
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX7
Peripheral Multiplexing
0x37
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX8
Peripheral Multiplexing
0x38
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX9
Peripheral Multiplexing
0x39
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
WRCONFIG
Write Configuration
0x28
32
write-only
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
22
1
HWSEL
Half-Word Select
31
1
INEN
Input Enable
17
1
PINMASK
Pin Mask for Multiple Pin Configuration
0
16
PMUX
Peripheral Multiplexing
24
4
PMUXEN
Peripheral Multiplexer Enable
16
1
PULLEN
Pull Enable
18
1
WRPINCFG
Write PINCFG
30
1
WRPMUX
Write PMUX
28
1
PORT_IOBUS
Port Module
PORT
0x0
0x0
0x80
registers
n
PORT
10
CTRL
Control
0x24
32
read-write
n
0x0
0x0
SAMPLING
Input Sampling Mode
0
32
DIR
Data Direction
0x0
32
read-write
n
0x0
0x0
DIR
Port Data Direction
0
32
DIRCLR
Data Direction Clear
0x4
32
read-write
n
0x0
0x0
DIRCLR
Port Data Direction Clear
0
32
DIRSET
Data Direction Set
0x8
32
read-write
n
0x0
0x0
DIRSET
Port Data Direction Set
0
32
DIRTGL
Data Direction Toggle
0xC
32
read-write
n
0x0
0x0
DIRTGL
Port Data Direction Toggle
0
32
EVCTRL
Event Input Control
0x2C
32
read-write
n
0x0
0x0
EVACT0
PORT Event Action 0
5
2
EVACT0Select
OUT
Event output to pin
0x0
SET
Set output register of pin on event
0x1
CLR
Clear output register of pin on event
0x2
TGL
Toggle output register of pin on event
0x3
EVACT1
PORT Event Action 1
13
2
EVACT2
PORT Event Action 2
21
2
EVACT3
PORT Event Action 3
29
2
PID0
PORT Event Pin Identifier 0
0
5
PID1
PORT Event Pin Identifier 1
8
5
PID2
PORT Event Pin Identifier 2
16
5
PID3
PORT Event Pin Identifier 3
24
5
PORTEI0
PORT Event Input Enable 0
7
1
PORTEI1
PORT Event Input Enable 1
15
1
PORTEI2
PORT Event Input Enable 2
23
1
PORTEI3
PORT Event Input Enable 3
31
1
IN
Data Input Value
0x20
32
read-only
n
0x0
0x0
IN
PORT Data Input Value
0
32
INTENCLR
Interrupt Enable Clear
0x60
32
read-write
n
0x0
0x0
NSCHK
Non-Secure Check Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x64
32
read-write
n
0x0
0x0
NSCHK
Non-Secure Check Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x68
32
read-write
n
0x0
0x0
NSCHK
Non-Secure Check
0
1
NONSEC
Security Attribution
0x6C
32
read-write
n
0x0
0x0
NONSEC
Port Security Attribution
0
32
NSCHK
Security Attribution Check
0x70
32
read-write
n
0x0
0x0
NSCHK
Port Security Attribution Check
0
32
OUT
Data Output Value
0x10
32
read-write
n
0x0
0x0
OUT
PORT Data Output Value
0
32
OUTCLR
Data Output Value Clear
0x14
32
read-write
n
0x0
0x0
OUTCLR
PORT Data Output Value Clear
0
32
OUTSET
Data Output Value Set
0x18
32
read-write
n
0x0
0x0
OUTSET
PORT Data Output Value Set
0
32
OUTTGL
Data Output Value Toggle
0x1C
32
read-write
n
0x0
0x0
OUTTGL
PORT Data Output Value Toggle
0
32
PINCFG0
Pin Configuration
0x40
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG1
Pin Configuration
0x41
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG10
Pin Configuration
0x4A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG11
Pin Configuration
0x4B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG12
Pin Configuration
0x4C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG13
Pin Configuration
0x4D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG14
Pin Configuration
0x4E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG15
Pin Configuration
0x4F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG16
Pin Configuration
0x50
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG17
Pin Configuration
0x51
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG18
Pin Configuration
0x52
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG19
Pin Configuration
0x53
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG2
Pin Configuration
0x42
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG20
Pin Configuration
0x54
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG21
Pin Configuration
0x55
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG22
Pin Configuration
0x56
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG23
Pin Configuration
0x57
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG24
Pin Configuration
0x58
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG25
Pin Configuration
0x59
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG26
Pin Configuration
0x5A
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG27
Pin Configuration
0x5B
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG28
Pin Configuration
0x5C
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG29
Pin Configuration
0x5D
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG3
Pin Configuration
0x43
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG30
Pin Configuration
0x5E
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG31
Pin Configuration
0x5F
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG4
Pin Configuration
0x44
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG5
Pin Configuration
0x45
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG6
Pin Configuration
0x46
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG7
Pin Configuration
0x47
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG8
Pin Configuration
0x48
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PINCFG9
Pin Configuration
0x49
8
read-write
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
6
1
INEN
Input Enable
1
1
PMUXEN
Peripheral Multiplexer Enable
0
1
PULLEN
Pull Enable
2
1
PMUX0
Peripheral Multiplexing
0x30
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX1
Peripheral Multiplexing
0x31
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX10
Peripheral Multiplexing
0x3A
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX11
Peripheral Multiplexing
0x3B
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX12
Peripheral Multiplexing
0x3C
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX13
Peripheral Multiplexing
0x3D
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX14
Peripheral Multiplexing
0x3E
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX15
Peripheral Multiplexing
0x3F
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX2
Peripheral Multiplexing
0x32
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX3
Peripheral Multiplexing
0x33
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX4
Peripheral Multiplexing
0x34
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX5
Peripheral Multiplexing
0x35
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX6
Peripheral Multiplexing
0x36
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX7
Peripheral Multiplexing
0x37
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX8
Peripheral Multiplexing
0x38
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUX9
Peripheral Multiplexing
0x39
8
read-write
n
0x0
0x0
PMUXE
Peripheral Multiplexing for Even-Numbered Pin
0
4
PMUXESelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
PMUXO
Peripheral Multiplexing for Odd-Numbered Pin
4
4
PMUXOSelect
A
Peripheral function A selected
0x0
B
Peripheral function B selected
0x1
C
Peripheral function C selected
0x2
D
Peripheral function D selected
0x3
E
Peripheral function E selected
0x4
F
Peripheral function F selected
0x5
G
Peripheral function G selected
0x6
H
Peripheral function H selected
0x7
I
Peripheral function I selected
0x8
WRCONFIG
Write Configuration
0x28
32
write-only
n
0x0
0x0
DRVSTR
Output Driver Strength Selection
22
1
HWSEL
Half-Word Select
31
1
INEN
Input Enable
17
1
PINMASK
Pin Mask for Multiple Pin Configuration
0
16
PMUX
Peripheral Multiplexing
24
4
PMUXEN
Peripheral Multiplexer Enable
16
1
PULLEN
Pull Enable
18
1
WRPINCFG
Write PINCFG
30
1
WRPMUX
Write PMUX
28
1
PTC
Peripheral Touch Controller
PTC
0x0
0x0
0x1
reserved
n
PTC
42
RSTC
Reset Controller
RSTC
0x0
0x0
0x1
registers
n
RCAUSE
Reset Cause
0x0
8
read-only
n
0x0
0x0
BOD12
Brown Out 1.2V Detector Reset
1
1
BOD33
Brown Out 3.3V Detector Reset
2
1
BODCORE
Brown Out CORE Detector Reset
1
1
BODVDD
Brown Out VDD Detector Reset
2
1
EXT
External Reset
4
1
POR
Power On Reset
0
1
SYST
System Reset Request
6
1
WDT
Watchdog Reset
5
1
RTC
Real-Time Counter
RTC
0x0
0x0
0x70
registers
n
RTC
2
ALARM
MODE2_ALARM Alarm n Value
0x20
32
read-write
n
0x0
0x0
DAY
Day
17
5
HOUR
Hour
12
5
HOURSelect
AM
Morning hour
0x00
PM
Afternoon hour
0x10
MINUTE
Minute
6
6
MONTH
Month
22
4
SECOND
Second
0
6
YEAR
Year
26
6
CLOCK
MODE2 Clock Value
0x18
32
read-write
n
0x0
0x0
DAY
Day
17
5
HOUR
Hour
12
5
MINUTE
Minute
6
6
MONTH
Month
22
4
SECOND
Second
0
6
YEAR
Year
26
6
COMP
MODE0 Compare n Value
0x20
32
read-write
n
0x0
0x0
COMP
Compare Value
0
32
COMP0
MODE1 Compare n Value
0x20
16
read-write
n
0x0
0x0
COMP
Compare Value
0
16
COMP1
MODE1 Compare n Value
0x22
16
read-write
n
0x0
0x0
COMP
Compare Value
0
16
COUNT
MODE0 Counter Value
0x18
32
read-write
n
0x0
0x0
COUNT
Counter Value
0
16
CTRLA
MODE1 Control A
0x0
16
read-write
n
0x0
0x0
CLKREP
Clock Representation
6
1
CLOCKSYNC
Clock Read Synchronization Enable
15
1
COUNTSYNC
Count Read Synchronization Enable
15
1
ENABLE
Enable
1
1
GPTRST
GP Registers Reset On Tamper Enable
14
1
MATCHCLR
Clear on Match
7
1
MODE
Operating Mode
2
2
MODESelect
COUNT32
Mode 0: 32-bit Counter
0
COUNT16
Mode 1: 16-bit Counter
1
CLOCK
Mode 2: Clock/Calendar
2
PRESCALER
Prescaler
8
4
PRESCALERSelect
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x0
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x2
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x3
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x4
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x5
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x6
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x7
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x8
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0x9
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xA
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xB
SWRST
Software Reset
0
1
CTRLB
MODE1 Control B
0x2
16
read-write
n
0x0
0x0
ACTF
Active Layer Frequency
12
3
ACTFSelect
DIV2
CLK_RTC_OUT = CLK_RTC/2
0x0
DIV4
CLK_RTC_OUT = CLK_RTC/4
0x1
DIV8
CLK_RTC_OUT = CLK_RTC/8
0x2
DIV16
CLK_RTC_OUT = CLK_RTC/16
0x3
DIV32
CLK_RTC_OUT = CLK_RTC/32
0x4
DIV64
CLK_RTC_OUT = CLK_RTC/64
0x5
DIV128
CLK_RTC_OUT = CLK_RTC/128
0x6
DIV256
CLK_RTC_OUT = CLK_RTC/256
0x7
DEBASYNC
Debouncer Asynchronous Enable
5
1
DEBF
Debounce Frequency
8
3
DEBFSelect
DIV2
CLK_RTC_DEB = CLK_RTC/2
0x0
DIV4
CLK_RTC_DEB = CLK_RTC/4
0x1
DIV8
CLK_RTC_DEB = CLK_RTC/8
0x2
DIV16
CLK_RTC_DEB = CLK_RTC/16
0x3
DIV32
CLK_RTC_DEB = CLK_RTC/32
0x4
DIV64
CLK_RTC_DEB = CLK_RTC/64
0x5
DIV128
CLK_RTC_DEB = CLK_RTC/128
0x6
DIV256
CLK_RTC_DEB = CLK_RTC/256
0x7
DEBMAJ
Debouncer Majority Enable
4
1
DMAEN
DMA Enable
7
1
GP0EN
General Purpose 0 Enable
0
1
RTCOUT
RTC Output Enable
6
1
SEPTO
Separate Tamper Outputs
15
1
DBGCTRL
Debug Control
0xE
8
read-write
n
0x0
0x0
DBGRUN
Run During Debug
0
1
EVCTRL
MODE1 Event Control
0x4
32
read-write
n
0x0
0x0
ALARMEO0
Alarm 0 Event Output Enable
8
1
CMPEO0
Compare 0 Event Output Enable
8
1
CMPEO1
Compare 1 Event Output Enable
9
1
OVFEO
Overflow Event Output Enable
15
1
PERDEO
Periodic Interval Daily Event Output Enable
24
1
PEREO0
Periodic Interval 0 Event Output Enable
0
1
PEREO1
Periodic Interval 1 Event Output Enable
1
1
PEREO2
Periodic Interval 2 Event Output Enable
2
1
PEREO3
Periodic Interval 3 Event Output Enable
3
1
PEREO4
Periodic Interval 4 Event Output Enable
4
1
PEREO5
Periodic Interval 5 Event Output Enable
5
1
PEREO6
Periodic Interval 6 Event Output Enable
6
1
PEREO7
Periodic Interval 7 Event Output Enable
7
1
TAMPEREO
Tamper Event Output Enable
14
1
TAMPEVEI
Tamper Event Input Enable
16
1
FREQCORR
Frequency Correction
0x14
8
read-write
n
0x0
0x0
SIGN
Correction Sign
7
1
VALUE
Correction Value
0
7
GP0
General Purpose
0x40
32
read-write
n
0x0
0x0
GP
General Purpose
0
32
GP1
General Purpose
0x44
32
read-write
n
0x0
0x0
GP
General Purpose
0
32
INTENCLR
MODE1 Interrupt Enable Clear
0x8
16
read-write
n
0x0
0x0
ALARM0
Alarm 0 Interrupt Enable
8
1
CMP0
Compare 0 Interrupt Enable
8
1
CMP1
Compare 1 Interrupt Enable
9
1
OVF
Overflow Interrupt Enable
15
1
PER0
Periodic Interval 0 Interrupt Enable
0
1
PER1
Periodic Interval 1 Interrupt Enable
1
1
PER2
Periodic Interval 2 Interrupt Enable
2
1
PER3
Periodic Interval 3 Interrupt Enable
3
1
PER4
Periodic Interval 4 Interrupt Enable
4
1
PER5
Periodic Interval 5 Interrupt Enable
5
1
PER6
Periodic Interval 6 Interrupt Enable
6
1
PER7
Periodic Interval 7 Interrupt Enable
7
1
TAMPER
Tamper Enable
14
1
INTENSET
MODE1 Interrupt Enable Set
0xA
16
read-write
n
0x0
0x0
ALARM0
Alarm 0 Interrupt Enable
8
1
CMP0
Compare 0 Interrupt Enable
8
1
CMP1
Compare 1 Interrupt Enable
9
1
OVF
Overflow Interrupt Enable
15
1
PER0
Periodic Interval 0 Enable
0
1
PER1
Periodic Interval 1 Enable
1
1
PER2
Periodic Interval 2 Enable
2
1
PER3
Periodic Interval 3 Enable
3
1
PER4
Periodic Interval 4 Enable
4
1
PER5
Periodic Interval 5 Enable
5
1
PER6
Periodic Interval 6 Enable
6
1
PER7
Periodic Interval 7 Enable
7
1
TAMPER
Tamper Enable
14
1
INTFLAG
MODE1 Interrupt Flag Status and Clear
0xC
16
read-write
n
0x0
0x0
ALARM0
Alarm 0
8
1
CMP0
Compare 0
8
1
CMP1
Compare 1
9
1
OVF
Overflow
15
1
PER0
Periodic Interval 0
0
1
PER1
Periodic Interval 1
1
1
PER2
Periodic Interval 2
2
1
PER3
Periodic Interval 3
3
1
PER4
Periodic Interval 4
4
1
PER5
Periodic Interval 5
5
1
PER6
Periodic Interval 6
6
1
PER7
Periodic Interval 7
7
1
TAMPER
Tamper
14
1
MASK
MODE2_ALARM Alarm n Mask
0x24
8
read-write
n
0x0
0x0
SEL
Alarm Mask Selection
0
3
SELSelect
OFF
Alarm Disabled
0x0
SS
Match seconds only
0x1
MMSS
Match seconds and minutes only
0x2
HHMMSS
Match seconds, minutes, and hours only
0x3
DDHHMMSS
Match seconds, minutes, hours, and days only
0x4
MMDDHHMMSS
Match seconds, minutes, hours, days, and months only
0x5
YYMMDDHHMMSS
Match seconds, minutes, hours, days, months, and years
0x6
PER
MODE1 Counter Period
0x1C
16
read-write
n
0x0
0x0
PER
Counter Period
0
16
SYNCBUSY
MODE1 Synchronization Busy Status
0x10
32
read-only
n
0x0
0x0
ALARM0
ALARM 0 Register Busy
5
1
CLOCK
CLOCK Register Busy
3
1
CLOCKSYNC
Clock Synchronization Enable Bit Busy
15
1
COMP0
COMP 0 Register Busy
5
1
COMP1
COMP 1 Register Busy
6
1
COUNT
COUNT Register Busy
3
1
COUNTSYNC
Count Synchronization Enable Bit Busy
15
1
ENABLE
Enable Bit Busy
1
1
FREQCORR
FREQCORR Register Busy
2
1
GP0
General Purpose 0 Register Busy
16
1
GP1
General Purpose 1 Register Busy
17
1
MASK0
MASK 0 Register Busy
11
1
PER
PER Register Busy
4
1
SWRST
Software Reset Bit Busy
0
1
TAMPCTRL
Tamper Control
0x60
32
read-write
n
0x0
0x0
DEBNC0
Debouncer Enable 0
24
1
DEBNC1
Debouncer Enable 1
25
1
DEBNC2
Debouncer Enable 2
26
1
DEBNC3
Debouncer Enable 3
27
1
IN0ACT
Tamper Input 0 Action
0
2
IN0ACTSelect
OFF
Off (Disabled)
0x0
WAKE
Wake without timestamp
0x1
CAPTURE
Capture timestamp
0x2
ACTL
Compare IN0 to OUT
0x3
IN1ACT
Tamper Input 1 Action
2
2
IN1ACTSelect
OFF
Off (Disabled)
0x0
WAKE
Wake without timestamp
0x1
CAPTURE
Capture timestamp
0x2
ACTL
Compare IN1 to OUT
0x3
IN2ACT
Tamper Input 2 Action
4
2
IN2ACTSelect
OFF
Off (Disabled)
0x0
WAKE
Wake without timestamp
0x1
CAPTURE
Capture timestamp
0x2
ACTL
Compare IN2 to OUT
0x3
IN3ACT
Tamper Input 3 Action
6
2
IN3ACTSelect
OFF
Off (Disabled)
0x0
WAKE
Wake without timestamp
0x1
CAPTURE
Capture timestamp
0x2
ACTL
Compare IN3 to OUT
0x3
TAMLVL0
Tamper Level Select 0
16
1
TAMLVL1
Tamper Level Select 1
17
1
TAMLVL2
Tamper Level Select 2
18
1
TAMLVL3
Tamper Level Select 3
19
1
TAMPCTRLB
Tamper Control B
0x6C
32
read-write
n
0x0
0x0
ALSI0
Active Layer Select Internal 0
0
1
ALSI1
Active Layer Select Internal 1
1
1
ALSI2
Active Layer Select Internal 2
2
1
ALSI3
Active Layer Select Internal 3
3
1
TAMPID
Tamper ID
0x68
32
read-write
n
0x0
0x0
TAMPEVT
Tamper Event Detected
31
1
TAMPID0
Tamper Input 0 Detected
0
1
TAMPID1
Tamper Input 1 Detected
1
1
TAMPID2
Tamper Input 2 Detected
2
1
TAMPID3
Tamper Input 3 Detected
3
1
TIMESTAMP
MODE1 Timestamp
0x64
32
read-only
n
0x0
0x0
COUNT
Count Timestamp Value
0
16
DAY
Day Timestamp Value
17
5
HOUR
Hour Timestamp Value
12
5
MINUTE
Minute Timestamp Value
6
6
MONTH
Month Timestamp Value
22
4
SECOND
Second Timestamp Value
0
6
YEAR
Year Timestamp Value
26
6
SCB
System Control Block
SCB
0x0
0x0
0x88
registers
n
AFSR
Auxiliary Fault Status Register
0x3C
32
read-write
n
0x0
0x0
AIRCR
Application Interrupt and Reset Control Register
0xC
32
read-write
n
0x0
0x0
BFHFNMINS
BusFault, HardFault and NMI Non-secure enable
13
1
BFHFNMINSSelect
SECURE
BusFault, HardFault, and NMI are Secure
0x0
NON_SECURE
BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault
0x1
ENDIANNESS
Data Endianness, 0=little, 1=big
15
1
ENDIANNESSSelect
LITTLE
Little-endian
0
BIG
Big-endian
1
PRIS
Prioritize Secure Exceptions
14
1
PRISSelect
SAME
Priority ranges of Secure and Non-secure exceptions are identical
0x0
NS_DEPRIO
Non-secure exceptions are de-prioritized
0x1
SYSRESETREQ
System Reset Request
2
1
SYSRESETREQSelect
NO
Do not request a system reset
0
YES
Request a system reset
1
SYSRESETREQS
System Reset Request Secure only
3
1
SYSRESETREQSSelect
BOTH
SYSRESETREQ functionality is available to both Security states
0x0
SECURE
SYSRESETREQ functionality is only available to Secure state
0x1
VECTCLRACTIVE
Debug: Clear Active State
1
1
VECTCLRACTIVESelect
NO
Do not clear active state
0x0
YES
Clear active state
0x1
VECTKEY
Register Key (0x05FA)
16
16
CCR
Configuration and Control Register
0x14
32
read-write
n
0x0
0x0
BFHFNMIGN
BusFault in HardFault or NMI ignore
8
1
BP
Branch prediction enable
18
1
DC
Data cache enable
16
1
DIV_0_TRP
Divide by zero trap
4
1
IC
Instruction cache enable
17
1
STKOFHFNMIGN
Stack overflow in HardFault and NMI ignore
10
1
UNALIGN_TRP
Unaligned trap
3
1
UNALIGN_TRPSelect
VALUE_0
Do not trap unaligned halfword and word accesses
0
VALUE_1
Trap unaligned halfword and word accesses
1
USERSETMPEND
User set main pending
1
1
CCSIDR
Current Cache Size ID register
0x80
32
read-only
n
0x0
0x0
Associativity
Associativity - 1
3
10
LineSize
log2(number of words per line) - 2
0
3
NumSets
Number of sets - 1
13
15
RA
Read-Allocate
29
1
WA
Write-Allocate
28
1
WB
Write-Back
30
1
WT
Write-Through
31
1
CLIDR
Cache Level ID Register
0x78
32
read-only
n
0x0
0x0
Ctype1
Cache type at level 1
0
3
Ctype1Select
NO
No cache
0
IC
Instruction cache only
1
DC
Data cache only
2
SEPARATE
Separate instruction and data caches
3
UNIFIED
Unified cache
4
Ctype2
Cache type at level 2
3
3
Ctype2Select
NO
No cache
0
IC
Instruction cache only
1
DC
Data cache only
2
SEPARATE
Separate instruction and data caches
3
UNIFIED
Unified cache
4
Ctype3
Cache type at level 3
6
3
Ctype3Select
NO
No cache
0
IC
Instruction cache only
1
DC
Data cache only
2
SEPARATE
Separate instruction and data caches
3
UNIFIED
Unified cache
4
Ctype4
Cache type at level 4
9
3
Ctype4Select
NO
No cache
0
IC
Instruction cache only
1
DC
Data cache only
2
SEPARATE
Separate instruction and data caches
3
UNIFIED
Unified cache
4
Ctype5
Cache type at level 5
12
3
Ctype5Select
NO
No cache
0
IC
Instruction cache only
1
DC
Data cache only
2
SEPARATE
Separate instruction and data caches
3
UNIFIED
Unified cache
4
Ctype6
Cache type at level 6
15
3
Ctype6Select
NO
No cache
0
IC
Instruction cache only
1
DC
Data cache only
2
SEPARATE
Separate instruction and data caches
3
UNIFIED
Unified cache
4
Ctype7
Cache type at level 7
18
3
Ctype7Select
NO
No cache
0
IC
Instruction cache only
1
DC
Data cache only
2
SEPARATE
Separate instruction and data caches
3
UNIFIED
Unified cache
4
ICB
Inner cache boundary
30
2
ICBSelect
NO
Not disclosed in this mechanism
0
L1
L1 cache is the highest inner level
1
L2
L2 cache is the highest inner level
2
L3
L3 cache is the highest inner level
3
LoC
Level of Coherence
24
3
LoUIS
Level of Unification Inner Shareable
21
3
LoUU
Level of Unification Uniprocessor
27
3
CPUID
CPUID base register
0x0
32
read-only
n
0x0
0x0
Architecture
Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line
16
4
Implementer
Implementer code, ARM=0x41
24
8
PartNo
Part number, 0xD20=Cortex-M23
4
12
Revision
Revision number
0
4
Variant
Variant number
20
4
CSSELR
Cache Size Selection Register
0x84
32
read-write
n
0x0
0x0
InD
Instruction not Data
0
1
Level
Cache level - 1
1
3
CTR
Cache Type Register
0x7C
32
read-only
n
0x0
0x0
CWG
Cache Write-back Granule
24
4
DminLine
Data cache minimum line length
16
4
ERG
Exclusives Reservation Granule
20
4
Format
Cache Type Register format
29
3
FormatSelect
NO
No cache type information provided
0
YES
Cache type information is provided
4
IminLine
Instruction cache minimum line length
0
4
DFSR
Debug Fault Status Register
0x30
32
read-write
n
0x0
0x0
BKPT
Breakpoint event
1
1
DWTTRAP
Watchpoint event
2
1
EXTERNAL
External event
4
1
HALTED
Halt or step event
0
1
VCATCH
Vector Catch event
3
1
ICSR
Interrupt Control and State Register
0x4
32
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending
22
1
ISRPREEMPT
Interrupt preempt
23
1
PENDNMICLR
Pend NMI clear
30
1
PENDNMISET
Pend NMI set
31
1
PENDNMISETSelect
VALUE_0
Write: no effect read: NMI exception is not pending
0
VALUE_1
Write: changes NMI exception state to pending read: NMI exception is pending
1
PENDSTCLR
Pend SysTick clear
25
1
PENDSTCLRSelect
VALUE_0
No effect
0
VALUE_1
Removes the pending state from the SysTick exception
1
PENDSTSET
Pend SysTick set
26
1
PENDSTSETSelect
VALUE_0
Write: no effect read: SysTick exception is not pending
0
VALUE_1
Write: changes SysTick exception state to pending read: SysTick exception is pending
1
PENDSVCLR
Pend PendSV clear
27
1
PENDSVCLRSelect
VALUE_0
No effect
0
VALUE_1
Removes the pending state from the PendSV exception
1
PENDSVSET
Pend PendSV set
28
1
PENDSVSETSelect
VALUE_0
Write: no effect read: PendSV exception is not pending
0
VALUE_1
Write: changes PendSV exception state to pending read: PendSV exception is pending
1
RETTOBASE
Return to base
11
1
VECTACTIVE
Vector active
0
9
VECTPENDING
Vector pending
12
9
SCR
System Control Register
0x10
32
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending bit
4
1
SEVONPENDSelect
VALUE_0
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
0
VALUE_1
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
1
SLEEPDEEP
Sleep deep
2
1
SLEEPDEEPSelect
VALUE_0
Sleep
0
VALUE_1
Deep sleep
1
SLEEPDEEPS
Sleep deep secure
3
1
SLEEPONEXIT
Sleep on exit
1
1
SLEEPONEXITSelect
VALUE_0
O not sleep when returning to Thread mode
0
VALUE_1
Enter sleep, or deep sleep, on return from an ISR
1
SHCSR
System Handler Control and State Register
0x24
32
read-write
n
0x0
0x0
HARDFAULTACT
HardFault exception active state
2
1
HARDFAULTPENDED
HardFault exception pended state
21
1
NMIACT
NMI exception active state
5
1
PENDSVACT
PendSV exception active state
10
1
SVCALLACT
SVCall exception active state
7
1
SVCALLPENDED
SVCall exception pended state
15
1
SYSTICKACT
SysTick exception active state
11
1
SHPR2
System Handler Priority Register 2
0x1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11, SVCall
24
8
SHPR3
System Handler Priority Register 3
0x20
32
read-write
n
0x0
0x0
PRI_12
Priority of system handler 12, DebugMonitor
0
8
PRI_14
Priority of system handler 14, PendSV
16
8
PRI_15
Priority of system handler 15, SysTick
24
8
VTOR
Vector Table Offset Register
0x8
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset
7
25
SERCOM0
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
SERCOM0_0
22
SERCOM0_1
23
SERCOM0_2
24
SERCOM0_OTHER
25
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud (LIN Slave) - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
USART_FRAME_ISO_7816
ISO 7816
0x7
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXINV
Receive Data Invert
10
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXINV
Transmit Data Invert
9
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
PAD3
PAD[0] = TxD PAD[1] = XCK PAD[2] = TE
0x3
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
LINCMD
LIN Command
24
2
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
CTRLC
USART_EXT Control C
0x8
32
read-write
n
0x0
0x0
BRKLEN
LIN Master Break Length
8
2
DSNACK
Disable Successive NACK
17
1
GTIME
Guard Time
0
3
HDRDLY
LIN Master Header Delay
10
2
INACK
Inhibit Not Acknowledge
16
1
MAXITER
Maximum Iterations
20
3
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
RXS
Receive Start Interrupt
3
1
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXERRCNT
USART_EXT Receive Error Count
0x20
8
read-only
n
0x0
0x0
RXERRCNT
Receive Error Count
0
8
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
DIR
Read/Write Direction
3
1
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
ITER
Maximum Number of Repetitions Reached
7
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
ENABLE
SERCOM Enable Synchronization Busy
1
1
RXERRCNT
RXERRCNT Synchronization Busy
3
1
SWRST
Software Reset Synchronization Busy
0
1
SYSOP
System Operation Synchronization Busy
2
1
SERCOM1
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
SERCOM1_0
26
SERCOM1_1
27
SERCOM1_2
28
SERCOM1_OTHER
29
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud (LIN Slave) - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
USART_FRAME_ISO_7816
ISO 7816
0x7
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXINV
Receive Data Invert
10
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXINV
Transmit Data Invert
9
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
PAD3
PAD[0] = TxD PAD[1] = XCK PAD[2] = TE
0x3
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
LINCMD
LIN Command
24
2
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
CTRLC
USART_EXT Control C
0x8
32
read-write
n
0x0
0x0
BRKLEN
LIN Master Break Length
8
2
DSNACK
Disable Successive NACK
17
1
GTIME
Guard Time
0
3
HDRDLY
LIN Master Header Delay
10
2
INACK
Inhibit Not Acknowledge
16
1
MAXITER
Maximum Iterations
20
3
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
RXS
Receive Start Interrupt
3
1
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXERRCNT
USART_EXT Receive Error Count
0x20
8
read-only
n
0x0
0x0
RXERRCNT
Receive Error Count
0
8
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
DIR
Read/Write Direction
3
1
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
ITER
Maximum Number of Repetitions Reached
7
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
ENABLE
SERCOM Enable Synchronization Busy
1
1
RXERRCNT
RXERRCNT Synchronization Busy
3
1
SWRST
Software Reset Synchronization Busy
0
1
SYSOP
System Operation Synchronization Busy
2
1
SERCOM2
Serial Communication Interface
SERCOM
0x0
0x0
0x31
registers
n
SERCOM2_0
30
SERCOM2_1
31
SERCOM2_2
32
SERCOM2_OTHER
33
ADDR
SPIS Address
0x24
32
read-write
n
0x0
0x0
ADDR
Address Value
0
8
ADDRMASK
Address Mask
16
8
GENCEN
General Call Address Enable
0
1
HS
High Speed Mode
14
1
LEN
Length
16
8
LENEN
Length Enable
13
1
TENBITEN
Ten Bit Addressing Enable
15
1
BAUD
USART_EXT Baud Rate
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
BAUDLOW
Baud Rate Value Low
8
8
HSBAUD
High Speed Baud Rate Value
16
8
HSBAUDLOW
High Speed Baud Rate Value Low
24
8
BAUD_FRACFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_FRAC_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
13
FP
Fractional Part
13
3
BAUD_USARTFP_MODE
USART_EXT Baud Rate
BAUD
0xC
16
read-write
n
0x0
0x0
BAUD
Baud Rate Value
0
16
CTRLA
USART_EXT Control A
0x0
32
read-write
n
0x0
0x0
CMODE
Communication Mode
28
1
CMODESelect
ASYNC
Asynchronous Communication
0x0
SYNC
Synchronous Communication
0x1
CPHA
Clock Phase
28
1
CPHASelect
LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x0
TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0x1
CPOL
Clock Polarity
29
1
CPOLSelect
IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x0
IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
0x1
DIPO
Data In Pinout
20
2
DIPOSelect
PAD0
SERCOM PAD[0]
0x0
PAD1
SERCOM PAD[1]
0x1
PAD2
SERCOM PAD[2]
0x2
PAD3
SERCOM PAD[3]
0x3
DOPO
Data Out Pinout
16
2
DOPOSelect
PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x0
PAD1
DO on PAD[2], SCK on PAD[3] and SS on PAD[1]
0x1
PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
0x2
PAD3
DO on PAD[0], SCK on PAD[3] and SS on PAD[1]
0x3
DORD
Data Order
30
1
DORDSelect
MSB
MSB is transmitted first
0x0
LSB
LSB is transmitted first
0x1
ENABLE
Enable
1
1
FORM
Frame Format
24
4
FORMSelect
SPI_FRAME
SPI Frame
0x0
USART_FRAME_NO_PARITY
USART frame
0x0
USART_FRAME_WITH_PARITY
USART frame with parity
0x1
SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x2
USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud (LIN Slave) - break detection and auto-baud
0x4
USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x5
USART_FRAME_ISO_7816
ISO 7816
0x7
IBON
Immediate Buffer Overflow Notification
8
1
INACTOUT
Inactive Time-Out
28
2
INACTOUTSelect
DISABLE
Disabled
0x0
55US
5-6 SCL Time-Out(50-60us)
0x1
105US
10-11 SCL Time-Out(100-110us)
0x2
205US
20-21 SCL Time-Out(200-210us)
0x3
LOWTOUTEN
SCL Low Timeout Enable
30
1
MEXTTOEN
Master SCL Low Extend Timeout
22
1
MODE
Operating Mode
2
3
MODESelect
USART_EXT_CLK
USART with external clock
0x0
USART_INT_CLK
USART with internal clock
0x1
SPI_SLAVE
SPI in slave operation
0x2
SPI_MASTER
SPI in master operation
0x3
I2C_SLAVE
I2C slave operation
0x4
I2C_MASTER
I2C master operation
0x5
PINOUT
Pin Usage
16
1
RUNSTDBY
Run during Standby
7
1
RXINV
Receive Data Invert
10
1
RXPO
Receive Data Pinout
20
2
RXPOSelect
PAD0
SERCOM PAD[0] is used for data reception
0x0
PAD1
SERCOM PAD[1] is used for data reception
0x1
PAD2
SERCOM PAD[2] is used for data reception
0x2
PAD3
SERCOM PAD[3] is used for data reception
0x3
SAMPA
Sample Adjustment
22
2
SAMPASelect
ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x0
ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x1
ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x2
ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
0x3
SAMPR
Sample
13
3
SAMPRSelect
16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x0
16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x1
8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x2
8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x3
3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
0x4
SCLSM
SCL Clock Stretch Mode
27
1
SDAHOLD
SDA Hold Time
20
2
SDAHOLDSelect
DISABLE
Disabled
0x0
75NS
50-100ns hold time
0x1
450NS
300-600ns hold time
0x2
600NS
400-800ns hold time
0x3
SEXTTOEN
Slave SCL Low Extend Timeout
23
1
SPEED
Transfer Speed
24
2
SPEEDSelect
STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x0
FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x1
HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
0x2
SWRST
Software Reset
0
1
TXINV
Transmit Data Invert
9
1
TXPO
Transmit Data Pinout
16
2
TXPOSelect
PAD0
PAD[0] = TxD PAD[1] = XCK
0x0
PAD1
PAD[2] = TxD PAD[3] = XCK
0x1
PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x2
PAD3
PAD[0] = TxD PAD[1] = XCK PAD[2] = TE
0x3
CTRLB
USART_EXT Control B
0x4
32
read-write
n
0x0
0x0
AACKEN
Automatic Address Acknowledge
10
1
ACKACT
Acknowledge Action
18
1
AMODE
Address Mode
14
2
AMODESelect
MASK
SPI Address mask
0x0
2_ADDRESSES
Two unique Addressess
0x1
RANGE
Address Range
0x2
CHSIZE
Character Size
0
3
CHSIZESelect
8_BIT
8 Bits
0x0
9_BIT
9 Bits
0x1
5_BIT
5 Bits
0x5
6_BIT
6 Bits
0x6
7_BIT
7 Bits
0x7
CMD
Command
16
2
COLDEN
Collision Detection Enable
8
1
ENC
Encoding Format
10
1
GCMD
PMBus Group Command
9
1
LINCMD
LIN Command
24
2
MSSEN
Master Slave Select Enable
13
1
PLOADEN
Data Preload Enable
6
1
PMODE
Parity Mode
13
1
PMODESelect
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
QCEN
Quick Command Enable
9
1
RXEN
Receiver Enable
17
1
SBMODE
Stop Bit Mode
6
1
SBMODESelect
1_BIT
One Stop Bit
0x0
2_BIT
Two Stop Bits
0x1
SFDE
Start of Frame Detection Enable
9
1
SMEN
Smart Mode Enable
8
1
SSDE
Slave Select Low Detect Enable
9
1
TXEN
Transmitter Enable
16
1
CTRLC
USART_EXT Control C
0x8
32
read-write
n
0x0
0x0
BRKLEN
LIN Master Break Length
8
2
DSNACK
Disable Successive NACK
17
1
GTIME
Guard Time
0
3
HDRDLY
LIN Master Header Delay
10
2
INACK
Inhibit Not Acknowledge
16
1
MAXITER
Maximum Iterations
20
3
DATA
USART_EXT Data
0x28
16
read-write
n
0x0
0x0
DATA
Data Value
0
9
DBGCTRL
USART_EXT Debug Control
0x30
8
read-write
n
0x0
0x0
DBGSTOP
Debug Mode
0
1
INTENCLR
USART_EXT Interrupt Enable Clear
0x14
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Disable
1
1
CTSIC
Clear To Send Input Change Interrupt Disable
4
1
DRDY
Data Interrupt Disable
2
1
DRE
Data Register Empty Interrupt Disable
0
1
ERROR
Combined Error Interrupt Disable
7
1
MB
Master On Bus Interrupt Disable
0
1
PREC
Stop Received Interrupt Disable
0
1
RXBRK
Break Received Interrupt Disable
5
1
RXC
Receive Complete Interrupt Disable
2
1
RXS
Receive Start Interrupt Disable
3
1
SB
Slave On Bus Interrupt Disable
1
1
SSL
Slave Select Low Interrupt Disable
3
1
TXC
Transmit Complete Interrupt Disable
1
1
INTENSET
USART_EXT Interrupt Enable Set
0x16
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt Enable
1
1
CTSIC
Clear To Send Input Change Interrupt Enable
4
1
DRDY
Data Interrupt Enable
2
1
DRE
Data Register Empty Interrupt Enable
0
1
ERROR
Combined Error Interrupt Enable
7
1
MB
Master On Bus Interrupt Enable
0
1
PREC
Stop Received Interrupt Enable
0
1
RXBRK
Break Received Interrupt Enable
5
1
RXC
Receive Complete Interrupt Enable
2
1
RXS
Receive Start Interrupt Enable
3
1
SB
Slave On Bus Interrupt Enable
1
1
SSL
Slave Select Low Interrupt Enable
3
1
TXC
Transmit Complete Interrupt Enable
1
1
INTFLAG
USART_EXT Interrupt Flag Status and Clear
0x18
8
read-write
n
0x0
0x0
AMATCH
Address Match Interrupt
1
1
CTSIC
Clear To Send Input Change Interrupt
4
1
DRDY
Data Interrupt
2
1
DRE
Data Register Empty Interrupt
0
1
ERROR
Combined Error Interrupt
7
1
MB
Master On Bus Interrupt
0
1
PREC
Stop Received Interrupt
0
1
RXBRK
Break Received Interrupt
5
1
RXC
Receive Complete Interrupt
2
1
RXS
Receive Start Interrupt
3
1
SB
Slave On Bus Interrupt
1
1
SSL
Slave Select Low Interrupt Flag
3
1
TXC
Transmit Complete Interrupt
1
1
RXERRCNT
USART_EXT Receive Error Count
0x20
8
read-only
n
0x0
0x0
RXERRCNT
Receive Error Count
0
8
RXPL
USART_EXT Receive Pulse Length
0xE
8
read-write
n
0x0
0x0
RXPL
Receive Pulse Length
0
8
STATUS
USART_EXT Status
0x1A
16
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost
1
1
BUFOVF
Buffer Overflow
2
1
BUSERR
Bus Error
0
1
BUSSTATE
Bus State
4
2
CLKHOLD
Clock Hold
7
1
COLL
Collision Detected
5
1
CTS
Clear To Send
3
1
DIR
Read/Write Direction
3
1
FERR
Frame Error
1
1
HS
High Speed
10
1
ISF
Inconsistent Sync Field
4
1
ITER
Maximum Number of Repetitions Reached
7
1
LENERR
Length Error
10
1
LOWTOUT
SCL Low Timeout
6
1
MEXTTOUT
Master SCL Low Extend Timeout
8
1
PERR
Parity Error
0
1
RXNACK
Received Not Acknowledge
2
1
SEXTTOUT
Slave SCL Low Extend Timeout
9
1
SR
Repeated Start
4
1
TXE
Transmitter Empty
6
1
SYNCBUSY
USART_EXT Synchronization Busy
0x1C
32
read-only
n
0x0
0x0
CTRLB
CTRLB Synchronization Busy
2
1
ENABLE
SERCOM Enable Synchronization Busy
1
1
RXERRCNT
RXERRCNT Synchronization Busy
3
1
SWRST
Software Reset Synchronization Busy
0
1
SYSOP
System Operation Synchronization Busy
2
1
SUPC
Supply Controller
SUPC
0x0
0x0
0x30
registers
n
0x0
0x30
registers
n
BOD12
BOD12 Control
0x14
32
read-write
n
0x0
0x0
ACTCFG
Configuration in Active mode
8
1
ACTION
Action when Threshold Crossed
3
2
ACTIONSelect
NONE
No action
0x0
RESET
The BOD12 generates a reset
0x1
INT
The BOD12 generates an interrupt
0x2
ENABLE
Enable
1
1
HYST
Hysteresis Enable
2
1
LEVEL
Threshold Level
16
6
PSEL
Prescaler Select
12
4
PSELSelect
DIV2
Divide clock by 2
0x0
DIV4
Divide clock by 4
0x1
DIV8
Divide clock by 8
0x2
DIV16
Divide clock by 16
0x3
DIV32
Divide clock by 32
0x4
DIV64
Divide clock by 64
0x5
DIV128
Divide clock by 128
0x6
DIV256
Divide clock by 256
0x7
DIV512
Divide clock by 512
0x8
DIV1024
Divide clock by 1024
0x9
DIV2048
Divide clock by 2048
0xA
DIV4096
Divide clock by 4096
0xB
DIV8192
Divide clock by 8192
0xC
DIV16384
Divide clock by 16384
0xD
DIV32768
Divide clock by 32768
0xE
DIV65536
Divide clock by 65536
0xF
RUNSTDBY
Run during Standby
6
1
STDBYCFG
Configuration in Standby mode
5
1
BOD33
BOD33 Control
0x10
32
read-write
n
0x0
0x0
ACTCFG
Configuration in Active mode
8
1
ACTION
Action when Threshold Crossed
3
2
ACTIONSelect
NONE
No action
0x0
RESET
The BOD33 generates a reset
0x1
INT
The BOD33 generates an interrupt
0x2
BKUP
The BOD33 puts the device in backup sleep mode if VMON=0
0x3
ENABLE
Enable
1
1
HYST
Hysteresis Enable
2
1
LEVEL
Threshold Level for VDD
16
6
PSEL
Prescaler Select
12
4
PSELSelect
DIV2
Divide clock by 2
0x0
DIV4
Divide clock by 4
0x1
DIV8
Divide clock by 8
0x2
DIV16
Divide clock by 16
0x3
DIV32
Divide clock by 32
0x4
DIV64
Divide clock by 64
0x5
DIV128
Divide clock by 128
0x6
DIV256
Divide clock by 256
0x7
DIV512
Divide clock by 512
0x8
DIV1024
Divide clock by 1024
0x9
DIV2048
Divide clock by 2048
0xA
DIV4096
Divide clock by 4096
0xB
DIV8192
Divide clock by 8192
0xC
DIV16384
Divide clock by 16384
0xD
DIV32768
Divide clock by 32768
0xE
DIV65536
Divide clock by 65536
0xF
REFSEL
BOD33 Voltage Reference Selection
11
1
REFSELSelect
SEL_VREFDETREF
Selects VREFDETREF for the BOD33
0
SEL_ULPVREF
Selects ULPVREF for the BOD33
1
RUNSTDBY
Run during Standby
6
1
STDBYCFG
Configuration in Standby mode
5
1
VREFSEL
BOD33 Voltage Reference Selection
11
1
VREFSELSelect
SEL_VREF
Selects VREF for the BOD33
0
SEL_ULPVREF
Selects ULPVREF for the BOD33
1
EVCTRL
Event Control
0x2C
32
read-write
n
0x0
0x0
BOD12DETEO
BOD12 Detection Event Output Enable
4
1
BOD33DETEO
BOD33 Detection Event Output Enable
1
1
INTENCLR
Interrupt Enable Clear
0x0
32
read-write
n
0x0
0x0
B12SRDY
BOD12 Synchronization Ready
5
1
B33SRDY
BOD33 Synchronization Ready
2
1
BOD12DET
BOD12 Detection
4
1
BOD12RDY
BOD12 Ready
3
1
BOD33DET
BOD33 Detection
1
1
BOD33RDY
BOD33 Ready
0
1
ULPVREFRDY
ULPVREF Voltage Reference Ready
11
1
VCORERDY
VDDCORE Ready
10
1
VREGRDY
Voltage Regulator Ready
8
1
INTENSET
Interrupt Enable Set
0x4
32
read-write
n
0x0
0x0
B12SRDY
BOD12 Synchronization Ready
5
1
B33SRDY
BOD33 Synchronization Ready
2
1
BOD12DET
BOD12 Detection
4
1
BOD12RDY
BOD12 Ready
3
1
BOD33DET
BOD33 Detection
1
1
BOD33RDY
BOD33 Ready
0
1
ULPVREFRDY
ULPVREF Voltage Reference Ready
11
1
VCORERDY
VDDCORE Ready
10
1
VREGRDY
Voltage Regulator Ready
8
1
INTFLAG
Interrupt Flag Status and Clear
0x8
32
read-write
n
0x0
0x0
B12SRDY
BOD12 Synchronization Ready
5
1
B33SRDY
BOD33 Synchronization Ready
2
1
BOD12DET
BOD12 Detection
4
1
BOD12RDY
BOD12 Ready
3
1
BOD33DET
BOD33 Detection
1
1
BOD33RDY
BOD33 Ready
0
1
ULPVREFRDY
ULPVREF Voltage Reference Ready
11
1
VCORERDY
VDDCORE Ready
10
1
VREGRDY
Voltage Regulator Ready
8
1
STATUS
Power and Clocks Status
0xC
32
read-only
n
0x0
0x0
B12SRDY
BOD12 Synchronization Ready
5
1
B33SRDY
BOD33 Synchronization Ready
2
1
BOD12DET
BOD12 Detection
4
1
BOD12RDY
BOD12 Ready
3
1
BOD33DET
BOD33 Detection
1
1
BOD33RDY
BOD33 Ready
0
1
ULPBIASRDY
Low Power Voltage Bias Ready
13
1
ULPVREFRDY
Low Power Voltage Reference Ready
12
1
VCORERDY
VDDCORE Ready
10
1
VREGRDY
Voltage Regulator Ready
8
1
VREF
VREF Control
0x1C
32
read-write
n
0x0
0x0
ONDEMAND
On Demand Control
7
1
RUNSTDBY
Run during Standby
6
1
SEL
Voltage Reference Selection
16
4
SELSelect
1V0
1.0V voltage reference typical value
0x0
1V1
1.1V voltage reference typical value
0x1
1V2
1.2V voltage reference typical value
0x2
1V25
1.25V voltage reference typical value
0x3
2V0
2.0V voltage reference typical value
0x4
2V2
2.2V voltage reference typical value
0x5
2V4
2.4V voltage reference typical value
0x6
2V5
2.5V voltage reference typical value
0x7
TSEN
Temperature Sensor Output Enable
1
1
TSSEL
Temperature Sensor Selection
3
1
VREFOE
Voltage Reference Output Enable
2
1
VREG
VREG Control
0x18
32
read-write
n
0x0
0x0
ENABLE
Enable
1
1
LPEFF
Low Power efficiency
8
1
RUNSTDBY
Run during Standby
6
1
SEL
Voltage Regulator Selection in active mode
2
2
SELSelect
LDO
LDO selection
0x0
BUCK
Buck selection
0x1
STDBYPL0
Standby in PL0
5
1
VREFSEL
Voltage Regulator Voltage Reference Selection
9
1
VREFSELSelect
SEL_VREF
Selects VREF for the VREG
0
SEL_ULPVREF
Selects ULPVREF for the VREG
1
VSPER
Voltage Scaling Period
24
8
VSVSTEP
Voltage Scaling Voltage Step
16
4
VREGSUSP
VREG Suspend Control
0x30
32
read-write
n
0x0
0x0
VREGSEN
Enable Voltage Regulator Suspend
0
1
SystemControl
System Control Registers
SystemControl
0x0
0x0
0xD34
registers
n
AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness, 0=little, 1=big
15
1
ENDIANNESSSelect
VALUE_0
Little-endian
0
VALUE_1
Big-endian
1
SYSRESETREQ
System Reset Request
2
1
SYSRESETREQSelect
VALUE_0
No system reset request
0
VALUE_1
Asserts a signal to the outer system that requests a reset
1
VECTCLRACTIVE
Debug: Clear state information
1
1
VECTKEY
Register key (0x05FA)
16
16
CCR
Configuration and Control Register
0xD14
32
read-only
n
0x0
0x0
STKALIGN
Stack 8-byte aligned on exception entry
9
1
STKALIGNSelect
VALUE_0
4-byte aligned
0
VALUE_1
8-byte aligned
1
UNALIGN_TRP
Unaligned accesses generates a Hard Fault
3
1
UNALIGN_TRPSelect
VALUE_0
Do not trap unaligned halfword and word accesses
0
VALUE_1
Trap unaligned halfword and word accesses
1
CPUID
CPUID Base Register
0xD00
32
read-only
n
0x0
0x0
ARCHITECTURE
Processor Architecture, 0xC=ARMv8-M BL
16
4
IMPLEMENTER
Implementer code, ARM=0x41
24
8
PARTNO
Processor Part Number, 0xD20=Cortex-M23
4
12
REVISION
Minor revision number
0
4
VARIANT
Major revision number
20
4
DFSR
Debug Fault Status Register
0xD30
32
read-write
n
0x0
0x0
BKPT
Breakpoint debug event
1
1
DWTTRAP
DWT debug event
2
1
EXTERNAL
EDBGRQ debug event
4
1
HALTED
Halt request debug event active
0
1
VCATCH
Vector catch debug event
3
1
ICSR
Interrupt Control and State Register
0xD04
32
read-write
n
0x0
0x0
ISRPENDING
Debug: NVIC interrupt pending
22
1
ISRPREEMPT
Debug: Pending exception serviced on exit from debug halt
23
1
NMIPENDSET
NMI set-pending bit
31
1
NMIPENDSETSelect
VALUE_0
Write: no effect read: NMI exception is not pending
0
VALUE_1
Write: changes NMI exception state to pending read: NMI exception is pending
1
PENDSTCLR
SysTick exception clear-pending bit
25
1
PENDSTCLRSelect
VALUE_0
No effect
0
VALUE_1
Removes the pending state from the SysTick exception
1
PENDSTSET
SysTick exception set-pending bit
26
1
PENDSTSETSelect
VALUE_0
Write: no effect read: SysTick exception is not pending
0
VALUE_1
Write: changes SysTick exception state to pending read: SysTick exception is pending
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVCLRSelect
VALUE_0
No effect
0
VALUE_1
Removes the pending state from the PendSV exception
1
PENDSVSET
PendSV set-pending bit
28
1
PENDSVSETSelect
VALUE_0
Write: no effect read: PendSV exception is not pending
0
VALUE_1
Write: changes PendSV exception state to pending read: PendSV exception is pending
1
VECTACTIVE
Debug: Exception number of currently executing exception, or 0 if thread mode
0
9
VECTPENDING
Exception number of the highest priority pending enabled exception
12
9
SCR
System Control Register
0xD10
32
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending bit
4
1
SEVONPENDSelect
VALUE_0
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
0
VALUE_1
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
1
SLEEPDEEP
Uses Deep Sleep as low power mode
2
1
SLEEPDEEPSelect
VALUE_0
Sleep
0
VALUE_1
Deep sleep
1
SLEEPONEXIT
Sleep-On-Exit when exiting Handler mode
1
1
SLEEPONEXITSelect
VALUE_0
O not sleep when returning to Thread mode
0
VALUE_1
Enter sleep, or deep sleep, on return from an ISR
1
SHCSR
System Handler Control and State Register
0xD24
32
read-write
n
0x0
0x0
SVCALLPENDED
15
1
SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11, SVCall
24
8
SHPR3
System Handler Priority Register 3
0xD20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14, PendSV
16
8
PRI_15
Priority of system handler 15, SysTick exception
24
8
VTOR
Vector Table Offset Register
0xD08
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset
7
25
SysTick
SysTick Timer
SysTick
0x0
0x0
0x10
registers
n
CALIB
SysTick Calibration Value Register
0xC
32
read-only
n
0x0
0x0
NOREF
No reference
31
1
NOREFSelect
VALUE_0
The reference clock is provided
0
VALUE_1
The reference clock is not provided
1
SKEW
Skew
30
1
SKEWSelect
VALUE_0
10ms calibration value is exact
0
VALUE_1
10ms calibration value is inexact, because of the clock frequency
1
TENMS
Ten milliseconds
0
24
CSR
SysTick Control and Status Register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
Clock source
2
1
CLKSOURCESelect
VALUE_0
External clock
0
VALUE_1
Processor clock
1
COUNTFLAG
Count flag
16
1
ENABLE
SysTick enable
0
1
ENABLESelect
VALUE_0
Counter disabled
0
VALUE_1
Counter enabled
1
TICKINT
Tick interrupt
1
1
TICKINTSelect
VALUE_0
Counting down to 0 does not assert the SysTick exception request
0
VALUE_1
Counting down to 0 asserts the SysTick exception request
1
CVR
SysTick Current Value Register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current counter value
24
1
RVR
SysTick Reload Value Register
0x4
32
read-write
n
0x0
0x0
RELOAD
Counter reload value
24
1
TC0
Basic Timer Counter
TC
0x0
0x0
0x38
registers
n
TC0
34
CC0
COUNT16 Compare and Capture
0x1C
16
read-write
n
0x0
0x0
CC
Counter/Compare Value
0
32
CC1
COUNT16 Compare and Capture
0x1E
16
read-write
n
0x0
0x0
CC
Counter/Compare Value
0
32
CCBUF0
COUNT16 Compare and Capture Buffer
0x30
16
read-write
n
0x0
0x0
CCBUF
Counter/Compare Buffer Value
0
32
CCBUF1
COUNT16 Compare and Capture Buffer
0x32
16
read-write
n
0x0
0x0
CCBUF
Counter/Compare Buffer Value
0
32
COUNT
COUNT16 Count
0x14
16
read-write
n
0x0
0x0
COUNT
Counter Value
0
32
CTRLA
Control A
0x0
32
read-write
n
0x0
0x0
ALOCK
Auto Lock
11
1
CAPTEN0
Capture Channel 0 Enable
16
1
CAPTEN1
Capture Channel 1 Enable
17
1
CAPTMODE0
Capture Mode Channel 0
24
2
CAPTMODE0Select
DEFAULT
Default capture
0
CAPTMIN
Minimum capture
1
CAPTMAX
Maximum capture
2
CAPTMODE1
Capture mode Channel 1
27
2
CAPTMODE1Select
DEFAULT
Default capture
0
CAPTMIN
Minimum capture
1
CAPTMAX
Maximum capture
2
COPEN0
Capture On Pin 0 Enable
20
1
COPEN1
Capture On Pin 1 Enable
21
1
ENABLE
Enable
1
1
MODE
Timer Counter Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
ONDEMAND
Clock On Demand
7
1
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0
DIV2
Prescaler: GCLK_TC/2
1
DIV4
Prescaler: GCLK_TC/4
2
DIV8
Prescaler: GCLK_TC/8
3
DIV16
Prescaler: GCLK_TC/16
4
DIV64
Prescaler: GCLK_TC/64
5
DIV256
Prescaler: GCLK_TC/256
6
DIV1024
Prescaler: GCLK_TC/1024
7
PRESCSYNC
Prescaler and Counter Synchronization
4
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock and reset the prescaler counter
2
RUNSTDBY
Run during Standby
6
1
SWRST
Software Reset
0
1
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
UPDATE
Force update of double-buffered register
3
READSYNC
Force a read synchronization of COUNT
4
DMAOS
One-shot DMA trigger
5
DIR
Counter Direction
0
1
LUPD
Lock Update
1
1
ONESHOT
One-Shot on Counter
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
UPDATE
Force update of double-buffered register
3
READSYNC
Force a read synchronization of COUNT
4
DMAOS
One-shot DMA trigger
5
DIR
Counter Direction
0
1
LUPD
Lock Update
1
1
ONESHOT
One-Shot on Counter
2
1
DBGCTRL
Debug Control
0xF
8
read-write
n
0x0
0x0
DBGRUN
Run During Debug
0
1
DRVCTRL
Control C
0xD
8
read-write
n
0x0
0x0
INVEN0
Output Waveform Invert Enable 0
0
1
INVEN1
Output Waveform Invert Enable 1
1
1
EVCTRL
Event Control
0x6
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
STAMP
Time stamp capture
4
PPW
Period catured in CC0, pulse width in CC1
5
PWP
Period catured in CC1, pulse width in CC0
6
PW
Pulse width capture
7
MCEO0
MC Event Output Enable 0
12
1
MCEO1
MC Event Output Enable 1
13
1
OVFEO
Event Output Enable
8
1
TCEI
TC Event Enable
5
1
TCINV
TC Event Input Polarity
4
1
INTENCLR
Interrupt Enable Clear
0x8
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Disable
1
1
MC0
MC Interrupt Disable 0
4
1
MC1
MC Interrupt Disable 1
5
1
OVF
OVF Interrupt Disable
0
1
INTENSET
Interrupt Enable Set
0x9
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Enable
1
1
MC0
MC Interrupt Enable 0
4
1
MC1
MC Interrupt Enable 1
5
1
OVF
OVF Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0xA
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Flag
1
1
MC0
MC Interrupt Flag 0
4
1
MC1
MC Interrupt Flag 1
5
1
OVF
OVF Interrupt Flag
0
1
PER
COUNT16 Period
0x1A
16
read-write
n
0x0
0x0
PER
Period Value
0
32
PERBUF
COUNT16 Period Buffer
0x2E
16
read-write
n
0x0
0x0
PERBUF
Period Buffer Value
0
32
STATUS
Status
0xB
8
read-write
n
0x0
0x0
CCBUFV0
Compare channel buffer 0 valid
4
1
CCBUFV1
Compare channel buffer 1 valid
5
1
PERBUFV
Synchronization Busy Status
3
1
SLAVE
Slave Status Flag
1
1
STOP
Stop Status Flag
0
1
SYNCBUSY
Synchronization Status
0x10
32
read-only
n
0x0
0x0
CC0
Compare Channel 0
6
1
CC1
Compare Channel 1
7
1
COUNT
Counter
4
1
CTRLB
CTRLB
2
1
ENABLE
enable
1
1
PER
Period
5
1
STATUS
STATUS
3
1
SWRST
swrst
0
1
WAVE
Waveform Generation Control
0xC
8
read-write
n
0x0
0x0
WAVEGEN
Waveform Generation Mode
0
2
WAVEGENSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
MPWM
Match PWM
3
TC1
Basic Timer Counter
TC
0x0
0x0
0x38
registers
n
TC1
35
CC0
COUNT16 Compare and Capture
0x1C
16
read-write
n
0x0
0x0
CC
Counter/Compare Value
0
32
CC1
COUNT16 Compare and Capture
0x1E
16
read-write
n
0x0
0x0
CC
Counter/Compare Value
0
32
CCBUF0
COUNT16 Compare and Capture Buffer
0x30
16
read-write
n
0x0
0x0
CCBUF
Counter/Compare Buffer Value
0
32
CCBUF1
COUNT16 Compare and Capture Buffer
0x32
16
read-write
n
0x0
0x0
CCBUF
Counter/Compare Buffer Value
0
32
COUNT
COUNT16 Count
0x14
16
read-write
n
0x0
0x0
COUNT
Counter Value
0
32
CTRLA
Control A
0x0
32
read-write
n
0x0
0x0
ALOCK
Auto Lock
11
1
CAPTEN0
Capture Channel 0 Enable
16
1
CAPTEN1
Capture Channel 1 Enable
17
1
CAPTMODE0
Capture Mode Channel 0
24
2
CAPTMODE0Select
DEFAULT
Default capture
0
CAPTMIN
Minimum capture
1
CAPTMAX
Maximum capture
2
CAPTMODE1
Capture mode Channel 1
27
2
CAPTMODE1Select
DEFAULT
Default capture
0
CAPTMIN
Minimum capture
1
CAPTMAX
Maximum capture
2
COPEN0
Capture On Pin 0 Enable
20
1
COPEN1
Capture On Pin 1 Enable
21
1
ENABLE
Enable
1
1
MODE
Timer Counter Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
ONDEMAND
Clock On Demand
7
1
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0
DIV2
Prescaler: GCLK_TC/2
1
DIV4
Prescaler: GCLK_TC/4
2
DIV8
Prescaler: GCLK_TC/8
3
DIV16
Prescaler: GCLK_TC/16
4
DIV64
Prescaler: GCLK_TC/64
5
DIV256
Prescaler: GCLK_TC/256
6
DIV1024
Prescaler: GCLK_TC/1024
7
PRESCSYNC
Prescaler and Counter Synchronization
4
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock and reset the prescaler counter
2
RUNSTDBY
Run during Standby
6
1
SWRST
Software Reset
0
1
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
UPDATE
Force update of double-buffered register
3
READSYNC
Force a read synchronization of COUNT
4
DMAOS
One-shot DMA trigger
5
DIR
Counter Direction
0
1
LUPD
Lock Update
1
1
ONESHOT
One-Shot on Counter
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
UPDATE
Force update of double-buffered register
3
READSYNC
Force a read synchronization of COUNT
4
DMAOS
One-shot DMA trigger
5
DIR
Counter Direction
0
1
LUPD
Lock Update
1
1
ONESHOT
One-Shot on Counter
2
1
DBGCTRL
Debug Control
0xF
8
read-write
n
0x0
0x0
DBGRUN
Run During Debug
0
1
DRVCTRL
Control C
0xD
8
read-write
n
0x0
0x0
INVEN0
Output Waveform Invert Enable 0
0
1
INVEN1
Output Waveform Invert Enable 1
1
1
EVCTRL
Event Control
0x6
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
STAMP
Time stamp capture
4
PPW
Period catured in CC0, pulse width in CC1
5
PWP
Period catured in CC1, pulse width in CC0
6
PW
Pulse width capture
7
MCEO0
MC Event Output Enable 0
12
1
MCEO1
MC Event Output Enable 1
13
1
OVFEO
Event Output Enable
8
1
TCEI
TC Event Enable
5
1
TCINV
TC Event Input Polarity
4
1
INTENCLR
Interrupt Enable Clear
0x8
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Disable
1
1
MC0
MC Interrupt Disable 0
4
1
MC1
MC Interrupt Disable 1
5
1
OVF
OVF Interrupt Disable
0
1
INTENSET
Interrupt Enable Set
0x9
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Enable
1
1
MC0
MC Interrupt Enable 0
4
1
MC1
MC Interrupt Enable 1
5
1
OVF
OVF Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0xA
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Flag
1
1
MC0
MC Interrupt Flag 0
4
1
MC1
MC Interrupt Flag 1
5
1
OVF
OVF Interrupt Flag
0
1
PER
COUNT16 Period
0x1A
16
read-write
n
0x0
0x0
PER
Period Value
0
32
PERBUF
COUNT16 Period Buffer
0x2E
16
read-write
n
0x0
0x0
PERBUF
Period Buffer Value
0
32
STATUS
Status
0xB
8
read-write
n
0x0
0x0
CCBUFV0
Compare channel buffer 0 valid
4
1
CCBUFV1
Compare channel buffer 1 valid
5
1
PERBUFV
Synchronization Busy Status
3
1
SLAVE
Slave Status Flag
1
1
STOP
Stop Status Flag
0
1
SYNCBUSY
Synchronization Status
0x10
32
read-only
n
0x0
0x0
CC0
Compare Channel 0
6
1
CC1
Compare Channel 1
7
1
COUNT
Counter
4
1
CTRLB
CTRLB
2
1
ENABLE
enable
1
1
PER
Period
5
1
STATUS
STATUS
3
1
SWRST
swrst
0
1
WAVE
Waveform Generation Control
0xC
8
read-write
n
0x0
0x0
WAVEGEN
Waveform Generation Mode
0
2
WAVEGENSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
MPWM
Match PWM
3
TC2
Basic Timer Counter
TC
0x0
0x0
0x38
registers
n
TC2
36
CC0
COUNT16 Compare and Capture
0x1C
16
read-write
n
0x0
0x0
CC
Counter/Compare Value
0
32
CC1
COUNT16 Compare and Capture
0x1E
16
read-write
n
0x0
0x0
CC
Counter/Compare Value
0
32
CCBUF0
COUNT16 Compare and Capture Buffer
0x30
16
read-write
n
0x0
0x0
CCBUF
Counter/Compare Buffer Value
0
32
CCBUF1
COUNT16 Compare and Capture Buffer
0x32
16
read-write
n
0x0
0x0
CCBUF
Counter/Compare Buffer Value
0
32
COUNT
COUNT16 Count
0x14
16
read-write
n
0x0
0x0
COUNT
Counter Value
0
32
CTRLA
Control A
0x0
32
read-write
n
0x0
0x0
ALOCK
Auto Lock
11
1
CAPTEN0
Capture Channel 0 Enable
16
1
CAPTEN1
Capture Channel 1 Enable
17
1
CAPTMODE0
Capture Mode Channel 0
24
2
CAPTMODE0Select
DEFAULT
Default capture
0
CAPTMIN
Minimum capture
1
CAPTMAX
Maximum capture
2
CAPTMODE1
Capture mode Channel 1
27
2
CAPTMODE1Select
DEFAULT
Default capture
0
CAPTMIN
Minimum capture
1
CAPTMAX
Maximum capture
2
COPEN0
Capture On Pin 0 Enable
20
1
COPEN1
Capture On Pin 1 Enable
21
1
ENABLE
Enable
1
1
MODE
Timer Counter Mode
2
2
MODESelect
COUNT16
Counter in 16-bit mode
0
COUNT8
Counter in 8-bit mode
1
COUNT32
Counter in 32-bit mode
2
ONDEMAND
Clock On Demand
7
1
PRESCALER
Prescaler
8
3
PRESCALERSelect
DIV1
Prescaler: GCLK_TC
0
DIV2
Prescaler: GCLK_TC/2
1
DIV4
Prescaler: GCLK_TC/4
2
DIV8
Prescaler: GCLK_TC/8
3
DIV16
Prescaler: GCLK_TC/16
4
DIV64
Prescaler: GCLK_TC/64
5
DIV256
Prescaler: GCLK_TC/256
6
DIV1024
Prescaler: GCLK_TC/1024
7
PRESCSYNC
Prescaler and Counter Synchronization
4
2
PRESCSYNCSelect
GCLK
Reload or reset the counter on next generic clock
0
PRESC
Reload or reset the counter on next prescaler clock
1
RESYNC
Reload or reset the counter on next generic clock and reset the prescaler counter
2
RUNSTDBY
Run during Standby
6
1
SWRST
Software Reset
0
1
CTRLBCLR
Control B Clear
0x4
8
read-write
n
0x0
0x0
CMD
Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
UPDATE
Force update of double-buffered register
3
READSYNC
Force a read synchronization of COUNT
4
DMAOS
One-shot DMA trigger
5
DIR
Counter Direction
0
1
LUPD
Lock Update
1
1
ONESHOT
One-Shot on Counter
2
1
CTRLBSET
Control B Set
0x5
8
read-write
n
0x0
0x0
CMD
Command
5
3
CMDSelect
NONE
No action
0
RETRIGGER
Force a start, restart or retrigger
1
STOP
Force a stop
2
UPDATE
Force update of double-buffered register
3
READSYNC
Force a read synchronization of COUNT
4
DMAOS
One-shot DMA trigger
5
DIR
Counter Direction
0
1
LUPD
Lock Update
1
1
ONESHOT
One-Shot on Counter
2
1
DBGCTRL
Debug Control
0xF
8
read-write
n
0x0
0x0
DBGRUN
Run During Debug
0
1
DRVCTRL
Control C
0xD
8
read-write
n
0x0
0x0
INVEN0
Output Waveform Invert Enable 0
0
1
INVEN1
Output Waveform Invert Enable 1
1
1
EVCTRL
Event Control
0x6
16
read-write
n
0x0
0x0
EVACT
Event Action
0
3
EVACTSelect
OFF
Event action disabled
0
RETRIGGER
Start, restart or retrigger TC on event
1
COUNT
Count on event
2
START
Start TC on event
3
STAMP
Time stamp capture
4
PPW
Period catured in CC0, pulse width in CC1
5
PWP
Period catured in CC1, pulse width in CC0
6
PW
Pulse width capture
7
MCEO0
MC Event Output Enable 0
12
1
MCEO1
MC Event Output Enable 1
13
1
OVFEO
Event Output Enable
8
1
TCEI
TC Event Enable
5
1
TCINV
TC Event Input Polarity
4
1
INTENCLR
Interrupt Enable Clear
0x8
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Disable
1
1
MC0
MC Interrupt Disable 0
4
1
MC1
MC Interrupt Disable 1
5
1
OVF
OVF Interrupt Disable
0
1
INTENSET
Interrupt Enable Set
0x9
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Enable
1
1
MC0
MC Interrupt Enable 0
4
1
MC1
MC Interrupt Enable 1
5
1
OVF
OVF Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0xA
8
read-write
n
0x0
0x0
ERR
ERR Interrupt Flag
1
1
MC0
MC Interrupt Flag 0
4
1
MC1
MC Interrupt Flag 1
5
1
OVF
OVF Interrupt Flag
0
1
PER
COUNT16 Period
0x1A
16
read-write
n
0x0
0x0
PER
Period Value
0
32
PERBUF
COUNT16 Period Buffer
0x2E
16
read-write
n
0x0
0x0
PERBUF
Period Buffer Value
0
32
STATUS
Status
0xB
8
read-write
n
0x0
0x0
CCBUFV0
Compare channel buffer 0 valid
4
1
CCBUFV1
Compare channel buffer 1 valid
5
1
PERBUFV
Synchronization Busy Status
3
1
SLAVE
Slave Status Flag
1
1
STOP
Stop Status Flag
0
1
SYNCBUSY
Synchronization Status
0x10
32
read-only
n
0x0
0x0
CC0
Compare Channel 0
6
1
CC1
Compare Channel 1
7
1
COUNT
Counter
4
1
CTRLB
CTRLB
2
1
ENABLE
enable
1
1
PER
Period
5
1
STATUS
STATUS
3
1
SWRST
swrst
0
1
WAVE
Waveform Generation Control
0xC
8
read-write
n
0x0
0x0
WAVEGEN
Waveform Generation Mode
0
2
WAVEGENSelect
NFRQ
Normal frequency
0
MFRQ
Match frequency
1
NPWM
Normal PWM
2
MPWM
Match PWM
3
TRAM
TrustRAM
TRAM
0x0
0x0
0x290
registers
n
TRAM
44
CTRLA
Control
0x0
8
read-write
n
0x0
0x0
DRP
Data Remanence Prevention
6
1
ENABLE
Enable
1
1
SILACC
Silent Access
7
1
SWRST
Software Reset
0
1
TAMPERS
Tamper Erase
4
1
DSCC
Data Scramble Control
0xC
32
write-only
n
0x0
0x0
DSCEN
Data Scramble Enable
31
1
DSCKEY
Data Scramble Key
0
30
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
DRP
Data Remanence Prevention Ended Interrupt Enable
1
1
ERR
TrustRAM Readout Error Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
DRP
Data Remanence Prevention Ended Interrupt Enable
1
1
ERR
TrustRAM Readout Error Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
DRP
Data Remanence Prevention Ended
1
1
ERR
TrustRAM Readout Error
0
1
PERMR
Permutation Read
0x11
8
read-only
n
0x0
0x0
DATA
Permutation Scrambler Data Output
0
3
PERMW
Permutation Write
0x10
8
write-only
n
0x0
0x0
DATA
Permutation Scrambler Data Input
0
3
RAM0
TrustRAM
0x100
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM1
TrustRAM
0x104
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM10
TrustRAM
0x128
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM11
TrustRAM
0x12C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM12
TrustRAM
0x130
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM13
TrustRAM
0x134
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM14
TrustRAM
0x138
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM15
TrustRAM
0x13C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM16
TrustRAM
0x140
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM17
TrustRAM
0x144
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM18
TrustRAM
0x148
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM19
TrustRAM
0x14C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM2
TrustRAM
0x108
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM20
TrustRAM
0x150
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM21
TrustRAM
0x154
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM22
TrustRAM
0x158
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM23
TrustRAM
0x15C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM24
TrustRAM
0x160
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM25
TrustRAM
0x164
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM26
TrustRAM
0x168
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM27
TrustRAM
0x16C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM28
TrustRAM
0x170
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM29
TrustRAM
0x174
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM3
TrustRAM
0x10C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM30
TrustRAM
0x178
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM31
TrustRAM
0x17C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM32
TrustRAM
0x180
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM33
TrustRAM
0x184
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM34
TrustRAM
0x188
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM35
TrustRAM
0x18C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM36
TrustRAM
0x190
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM37
TrustRAM
0x194
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM38
TrustRAM
0x198
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM39
TrustRAM
0x19C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM4
TrustRAM
0x110
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM40
TrustRAM
0x1A0
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM41
TrustRAM
0x1A4
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM42
TrustRAM
0x1A8
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM43
TrustRAM
0x1AC
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM44
TrustRAM
0x1B0
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM45
TrustRAM
0x1B4
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM46
TrustRAM
0x1B8
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM47
TrustRAM
0x1BC
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM48
TrustRAM
0x1C0
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM49
TrustRAM
0x1C4
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM5
TrustRAM
0x114
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM50
TrustRAM
0x1C8
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM51
TrustRAM
0x1CC
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM52
TrustRAM
0x1D0
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM53
TrustRAM
0x1D4
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM54
TrustRAM
0x1D8
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM55
TrustRAM
0x1DC
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM56
TrustRAM
0x1E0
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM57
TrustRAM
0x1E4
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM58
TrustRAM
0x1E8
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM59
TrustRAM
0x1EC
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM6
TrustRAM
0x118
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM60
TrustRAM
0x1F0
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM61
TrustRAM
0x1F4
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM62
TrustRAM
0x1F8
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM63
TrustRAM
0x1FC
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM7
TrustRAM
0x11C
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM8
TrustRAM
0x120
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM9
TrustRAM
0x124
32
read-write
n
0x0
0x0
DATA
Trust RAM Data
0
32
RAM_BYTE_MODE0
TrustRAM
RAM[%s]
0x100
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE1
TrustRAM
RAM[%s]
0x104
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE10
TrustRAM
RAM[%s]
0x128
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE11
TrustRAM
RAM[%s]
0x12C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE12
TrustRAM
RAM[%s]
0x130
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE13
TrustRAM
RAM[%s]
0x134
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE14
TrustRAM
RAM[%s]
0x138
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE15
TrustRAM
RAM[%s]
0x13C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE16
TrustRAM
RAM[%s]
0x140
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE17
TrustRAM
RAM[%s]
0x144
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE18
TrustRAM
RAM[%s]
0x148
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE19
TrustRAM
RAM[%s]
0x14C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE2
TrustRAM
RAM[%s]
0x108
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE20
TrustRAM
RAM[%s]
0x150
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE21
TrustRAM
RAM[%s]
0x154
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE22
TrustRAM
RAM[%s]
0x158
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE23
TrustRAM
RAM[%s]
0x15C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE24
TrustRAM
RAM[%s]
0x160
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE25
TrustRAM
RAM[%s]
0x164
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE26
TrustRAM
RAM[%s]
0x168
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE27
TrustRAM
RAM[%s]
0x16C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE28
TrustRAM
RAM[%s]
0x170
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE29
TrustRAM
RAM[%s]
0x174
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE3
TrustRAM
RAM[%s]
0x10C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE30
TrustRAM
RAM[%s]
0x178
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE31
TrustRAM
RAM[%s]
0x17C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE32
TrustRAM
RAM[%s]
0x180
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE33
TrustRAM
RAM[%s]
0x184
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE34
TrustRAM
RAM[%s]
0x188
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE35
TrustRAM
RAM[%s]
0x18C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE36
TrustRAM
RAM[%s]
0x190
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE37
TrustRAM
RAM[%s]
0x194
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE38
TrustRAM
RAM[%s]
0x198
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE39
TrustRAM
RAM[%s]
0x19C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE4
TrustRAM
RAM[%s]
0x110
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE40
TrustRAM
RAM[%s]
0x1A0
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE41
TrustRAM
RAM[%s]
0x1A4
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE42
TrustRAM
RAM[%s]
0x1A8
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE43
TrustRAM
RAM[%s]
0x1AC
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE44
TrustRAM
RAM[%s]
0x1B0
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE45
TrustRAM
RAM[%s]
0x1B4
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE46
TrustRAM
RAM[%s]
0x1B8
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE47
TrustRAM
RAM[%s]
0x1BC
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE48
TrustRAM
RAM[%s]
0x1C0
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE49
TrustRAM
RAM[%s]
0x1C4
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE5
TrustRAM
RAM[%s]
0x114
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE50
TrustRAM
RAM[%s]
0x1C8
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE51
TrustRAM
RAM[%s]
0x1CC
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE52
TrustRAM
RAM[%s]
0x1D0
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE53
TrustRAM
RAM[%s]
0x1D4
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE54
TrustRAM
RAM[%s]
0x1D8
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE55
TrustRAM
RAM[%s]
0x1DC
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE56
TrustRAM
RAM[%s]
0x1E0
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE57
TrustRAM
RAM[%s]
0x1E4
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE58
TrustRAM
RAM[%s]
0x1E8
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE59
TrustRAM
RAM[%s]
0x1EC
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE6
TrustRAM
RAM[%s]
0x118
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE60
TrustRAM
RAM[%s]
0x1F0
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE61
TrustRAM
RAM[%s]
0x1F4
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE62
TrustRAM
RAM[%s]
0x1F8
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE63
TrustRAM
RAM[%s]
0x1FC
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE7
TrustRAM
RAM[%s]
0x11C
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE8
TrustRAM
RAM[%s]
0x120
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_BYTE_MODE9
TrustRAM
RAM[%s]
0x124
32
read-write
n
0x0
0x0
BYTE0
Trust RAM Data
0
8
BYTE1
Trust RAM Data
8
8
BYTE2
Trust RAM Data
16
8
BYTE3
Trust RAM Data
24
8
RAM_HALFWORD_MODE0
TrustRAM
RAM[%s]
0x100
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE1
TrustRAM
RAM[%s]
0x104
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE10
TrustRAM
RAM[%s]
0x128
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE11
TrustRAM
RAM[%s]
0x12C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE12
TrustRAM
RAM[%s]
0x130
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE13
TrustRAM
RAM[%s]
0x134
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE14
TrustRAM
RAM[%s]
0x138
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE15
TrustRAM
RAM[%s]
0x13C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE16
TrustRAM
RAM[%s]
0x140
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE17
TrustRAM
RAM[%s]
0x144
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE18
TrustRAM
RAM[%s]
0x148
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE19
TrustRAM
RAM[%s]
0x14C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE2
TrustRAM
RAM[%s]
0x108
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE20
TrustRAM
RAM[%s]
0x150
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE21
TrustRAM
RAM[%s]
0x154
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE22
TrustRAM
RAM[%s]
0x158
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE23
TrustRAM
RAM[%s]
0x15C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE24
TrustRAM
RAM[%s]
0x160
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE25
TrustRAM
RAM[%s]
0x164
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE26
TrustRAM
RAM[%s]
0x168
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE27
TrustRAM
RAM[%s]
0x16C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE28
TrustRAM
RAM[%s]
0x170
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE29
TrustRAM
RAM[%s]
0x174
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE3
TrustRAM
RAM[%s]
0x10C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE30
TrustRAM
RAM[%s]
0x178
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE31
TrustRAM
RAM[%s]
0x17C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE32
TrustRAM
RAM[%s]
0x180
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE33
TrustRAM
RAM[%s]
0x184
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE34
TrustRAM
RAM[%s]
0x188
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE35
TrustRAM
RAM[%s]
0x18C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE36
TrustRAM
RAM[%s]
0x190
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE37
TrustRAM
RAM[%s]
0x194
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE38
TrustRAM
RAM[%s]
0x198
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE39
TrustRAM
RAM[%s]
0x19C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE4
TrustRAM
RAM[%s]
0x110
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE40
TrustRAM
RAM[%s]
0x1A0
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE41
TrustRAM
RAM[%s]
0x1A4
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE42
TrustRAM
RAM[%s]
0x1A8
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE43
TrustRAM
RAM[%s]
0x1AC
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE44
TrustRAM
RAM[%s]
0x1B0
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE45
TrustRAM
RAM[%s]
0x1B4
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE46
TrustRAM
RAM[%s]
0x1B8
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE47
TrustRAM
RAM[%s]
0x1BC
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE48
TrustRAM
RAM[%s]
0x1C0
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE49
TrustRAM
RAM[%s]
0x1C4
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE5
TrustRAM
RAM[%s]
0x114
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE50
TrustRAM
RAM[%s]
0x1C8
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE51
TrustRAM
RAM[%s]
0x1CC
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE52
TrustRAM
RAM[%s]
0x1D0
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE53
TrustRAM
RAM[%s]
0x1D4
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE54
TrustRAM
RAM[%s]
0x1D8
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE55
TrustRAM
RAM[%s]
0x1DC
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE56
TrustRAM
RAM[%s]
0x1E0
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE57
TrustRAM
RAM[%s]
0x1E4
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE58
TrustRAM
RAM[%s]
0x1E8
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE59
TrustRAM
RAM[%s]
0x1EC
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE6
TrustRAM
RAM[%s]
0x118
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE60
TrustRAM
RAM[%s]
0x1F0
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE61
TrustRAM
RAM[%s]
0x1F4
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE62
TrustRAM
RAM[%s]
0x1F8
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE63
TrustRAM
RAM[%s]
0x1FC
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE7
TrustRAM
RAM[%s]
0x11C
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE8
TrustRAM
RAM[%s]
0x120
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
RAM_HALFWORD_MODE9
TrustRAM
RAM[%s]
0x124
32
read-write
n
0x0
0x0
HWORD0
Trust RAM Halfword Data
0
16
HWORD1
Trust RAM Halfword Data
16
16
STATUS
Status
0x7
8
read-only
n
0x0
0x0
DRP
Data Remanence Prevention Ongoing
1
1
RAMINV
RAM Inversion Bit
0
1
SYNCBUSY
Synchronization Busy Status
0x8
32
read-only
n
0x0
0x0
ENABLE
Enable Busy
1
1
SWRST
Software Reset Busy
0
1
TRNG
True Random Generator
TRNG
0x0
0x0
0x24
registers
n
TRNG
43
CTRLA
Control A
0x0
8
read-write
n
0x0
0x0
ENABLE
Enable
1
1
RUNSTDBY
Run in Standby
6
1
DATA
Output Data
0x20
32
read-only
n
0x0
0x0
DATA
Output Data
0
32
EVCTRL
Event Control
0x4
8
read-write
n
0x0
0x0
DATARDYEO
Data Ready Event Output
0
1
INTENCLR
Interrupt Enable Clear
0x8
8
read-write
n
0x0
0x0
DATARDY
Data Ready Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x9
8
read-write
n
0x0
0x0
DATARDY
Data Ready Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0xA
8
read-write
n
0x0
0x0
DATARDY
Data Ready Interrupt Flag
0
1
WDT
Watchdog Timer
WDT
0x0
0x0
0xD
registers
n
WDT
1
CLEAR
Clear
0xC
8
write-only
n
0x0
0x0
CLEAR
Watchdog Clear
0
8
CLEARSelect
KEY
Clear Key
0xA5
CONFIG
Configuration
0x1
8
read-write
n
0x0
0x0
PER
Time-Out Period
0
4
PERSelect
CYC8
8 clock cycles
0x0
CYC16
16 clock cycles
0x1
CYC32
32 clock cycles
0x2
CYC64
64 clock cycles
0x3
CYC128
128 clock cycles
0x4
CYC256
256 clock cycles
0x5
CYC512
512 clock cycles
0x6
CYC1024
1024 clock cycles
0x7
CYC2048
2048 clock cycles
0x8
CYC4096
4096 clock cycles
0x9
CYC8192
8192 clock cycles
0xA
CYC16384
16384 clock cycles
0xB
WINDOW
Window Mode Time-Out Period
4
4
WINDOWSelect
CYC8
8 clock cycles
0x0
CYC16
16 clock cycles
0x1
CYC32
32 clock cycles
0x2
CYC64
64 clock cycles
0x3
CYC128
128 clock cycles
0x4
CYC256
256 clock cycles
0x5
CYC512
512 clock cycles
0x6
CYC1024
1024 clock cycles
0x7
CYC2048
2048 clock cycles
0x8
CYC4096
4096 clock cycles
0x9
CYC8192
8192 clock cycles
0xA
CYC16384
16384 clock cycles
0xB
CTRLA
Control
0x0
8
read-write
n
0x0
0x0
ALWAYSON
Always-On
7
1
ENABLE
Enable
1
1
RUNSTDBY
Run During Standby
6
1
WEN
Watchdog Timer Window Mode Enable
2
1
EWCTRL
Early Warning Interrupt Control
0x2
8
read-write
n
0x0
0x0
EWOFFSET
Early Warning Interrupt Time Offset
0
4
EWOFFSETSelect
CYC8
8 clock cycles
0x0
CYC16
16 clock cycles
0x1
CYC32
32 clock cycles
0x2
CYC64
64 clock cycles
0x3
CYC128
128 clock cycles
0x4
CYC256
256 clock cycles
0x5
CYC512
512 clock cycles
0x6
CYC1024
1024 clock cycles
0x7
CYC2048
2048 clock cycles
0x8
CYC4096
4096 clock cycles
0x9
CYC8192
8192 clock cycles
0xA
CYC16384
16384 clock cycles
0xB
INTENCLR
Interrupt Enable Clear
0x4
8
read-write
n
0x0
0x0
EW
Early Warning Interrupt Enable
0
1
INTENSET
Interrupt Enable Set
0x5
8
read-write
n
0x0
0x0
EW
Early Warning Interrupt Enable
0
1
INTFLAG
Interrupt Flag Status and Clear
0x6
8
read-write
n
0x0
0x0
EW
Early Warning
0
1
SYNCBUSY
Synchronization Busy
0x8
32
read-only
n
0x0
0x0
ALWAYSON
Always-On Synchronization Busy
4
1
CLEAR
Clear Synchronization Busy
5
1
ENABLE
Enable Synchronization Busy
1
1
RUNSTDBY
Run During Standby Synchronization Busy
3
1
WEN
Window Enable Synchronization Busy
2
1